_primary.vhd

来自「一个串口的完整FPGA工程」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity division is
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        factor          : in     vl_logic_vector(11 downto 0);
        tick_out        : out    vl_logic;
        enable          : in     vl_logic
    );
end division;