uart.map.summary

来自「一个串口的完整FPGA工程」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Thu May 07 23:21:45 2009
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : uart
Top-level Entity Name : top
Family : Cyclone
Total logic elements : 241
Total pins : 25
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : 0
Total DLLs : N/A until Partition Merge