coreofcpu.plg

来自「几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码」· PLG 代码 · 共 20 行

@P:  Worst Slack : 0.478
@P:  cpu|clk - Estimated Frequency : 72.4 MHz
@P:  cpu|clk - Requested Frequency : 70.0 MHz
@P:  cpu|clk - Estimated Period : 13.808
@P:  cpu|clk - Requested Period : 14.286
@P:  cpu|clk - Slack : 0.478
@P:  System - Estimated Frequency : 171.0 MHz
@P:  System - Requested Frequency : 70.0 MHz
@P:  System - Estimated Period : 5.849
@P:  System - Requested Period : 14.286
@P:  System - Slack : 8.437
@P: cpu Part : xc2vp2fg256-5
@P: cpu I/O primitives : 34
@P: cpu I/O Register bits : 0
@P: cpu Register bits (Non I/O) : 1409 (50%)
@P: cpu Single Port Rams (RAM32X8S) : 4
@P: cpu Dual Port Rams (RAM32X1D) : 32
@P: cpu 256x1 ROMs (ROM256X1) : 32
@P: cpu Total Luts : 2339 (83%)