coreofcpu.srr

几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码

U2.G_70                        LUT2      O        Out     0.891     5.390          
un6_shiftcnt_c2                Net                                              3  
U2.G_74                        LUT3      I1       In                5.390          
U2.G_74                        LUT3      O        Out     1.148     6.538          
un6_shiftcnt_c4                Net                                              5  
U2.shiftcnt_3_fast_fast[4]     LUT3      I2       In                6.538          
U2.shiftcnt_3_fast_fast[4]     LUT3      O        Out     1.148     7.687          
shiftcnt_3_iso_fast[4]         Net                                              7  
U2.shiftin_13[15]              MUXF5     S        In                7.687          
U2.shiftin_13[15]              MUXF5     O        Out     1.425     9.112          
shiftin_13[15]                 Net                                              3  
U2.shiftin_16[7]               LUT3      I1       In                9.112          
U2.shiftin_16[7]               LUT3      O        Out     0.791     9.903          
shiftin_16[7]                  Net                                              2  
U2.shiftin_19[7]               LUT3      I0       In                9.903          
U2.shiftin_19[7]               LUT3      O        Out     0.891     10.793         
shiftin_19[7]                  Net                                              3  
U2.shiftin_22[5]               LUT3      I1       In                10.793         
U2.shiftin_22[5]               LUT3      O        Out     0.791     11.584         
shiftin_22[5]                  Net                                              2  
U2.alu_out_0[5]                LUT3      I0       In                11.584         
U2.alu_out_0[5]                LUT3      O        Out     0.723     12.307         
alu_out_0[5]                   Net                                              1  
U2.alu_out_bm[5]               LUT3      I2       In                12.307         
U2.alu_out_bm[5]               LUT3      O        Out     0.723     13.030         
alu_out_bm[5]                  Net                                              1  
U2.alu_out[5]                  MUXF5     I1       In                13.030         
U2.alu_out[5]                  MUXF5     O        Out     0.494     13.524         
alu_result[5]                  Net                                              1  
exmem_out.alu_result[5]        FDR       D        In                13.524         
===================================================================================




====================================
Detailed Report for Clock: System
====================================



Starting Points with worst slack 
********************************

                                          Arrival          
Instance     Type     Pin       Net       Time        Slack
                                                           
-----------------------------------------------------------
reset        Port     reset     reset     0.000       8.437
===========================================================


Ending Points with worst slack 
******************************

                                                        Required          
Instance                   Type     Pin     Net         Time         Slack
                                                                          
--------------------------------------------------------------------------
idex_out.read_data2[0]     FDS      D       G_12174     14.376       8.437
idex_out.read_data2[1]     FDS      D       G_12175     14.376       8.437
idex_out.read_data2[2]     FDS      D       G_12176     14.376       8.437
idex_out.read_data2[3]     FDS      D       G_12177     14.376       8.437
idex_out.read_data2[4]     FDS      D       G_12178     14.376       8.437
idex_out.read_data2[5]     FDS      D       G_12179     14.376       8.437
idex_out.read_data2[6]     FDS      D       G_12180     14.376       8.437
idex_out.read_data2[7]     FDS      D       G_12181     14.376       8.437
idex_out.read_data2[8]     FDS      D       G_12159     14.376       8.437
idex_out.read_data2[9]     FDS      D       G_12160     14.376       8.437
==========================================================================



Worst Paths Information
***********************


Path information for path number 1: 
    - Setup time:                         -0.090
    = Required time:                      14.376

    - Propagation  time:                  5.939
    = Slack (non-critical) :              8.437

    Starting point:                       reset / reset
    Ending point:                         idex_out.read_data2[23] / D
    The start point is clocked by         cpu|clk [rising]
    The end   point is clocked by         cpu|clk [rising] on pin C

Instance / Net                         Pin       Pin               Arrival     Fan
Name                        Type       Name      Dir     Delay     Time        Out
----------------------------------------------------------------------------------
reset                       Port       reset     In      0.000     0.000          
reset                       Net                                                1  
reset_ibuf                  IBUF       I         In                0.000          
reset_ibuf                  IBUF       O         Out     1.712     1.712          
reset_c                     Net                                                5  
reset_c_3                   BUF        I         In                1.712          
reset_c_3                   BUF        O         Out     2.030     3.743          
reset_c_3                   Net                                                90 
G_9191                      LUT2       I0        In                3.743          
G_9191                      LUT2       O         Out     1.822     5.565          
G_9191                      Net                                                32 
G_12150                     LUT4_L     I1        In                5.565          
G_12150                     LUT4_L     LO        Out     0.374     5.939          
G_12150                     Net                                                1  
idex_out.read_data2[23]     FDS        D         In                5.939          
==================================================================================




##### END TIMING REPORT #####

---------------------------------------
Resource Usage Report for cpu 

Mapping to part: xc2vp2fg256-5
Cell usage:
BUF             5 uses
FD              32 uses
FDE             992 uses
FDE_1           32 uses
FDR             265 uses
FDS             40 uses
FD_1            48 uses
GND             4 uses
LDCP            13 uses
MUXCY_L         41 uses
MUXF5           279 uses
MUXF6           64 uses
RAM32X1D        32 uses
RAM32X8S        4 uses
VCC             3 uses
XORCY           41 uses

I/O primitives:
IBUF           33 uses
OBUF_F_24      1 use

BUFGP          1 use

I/O Register bits:                  0
Register bits not including I/Os:   1409 (50%)

Internal tri-state buffer usage summary
BUFTs + BUFEs: 46 of 704 (6%)

RAM/ROM usage summary
Single Port Rams (RAM32X8S): 4
Dual Port Rams (RAM32X1D): 32
256x1 ROMs (ROM256X1): 32


Global Clock Buffers: 1 of 16 (6%)


Mapping Summary:
Total  LUTs: 2339 (83%)

Mapper successful!
Process took 285.15 seconds realtime, 285.17 seconds cputime