coreofcpu.srr

几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码

*******************


Worst slack in design: 0.478

                   Requested     Estimated     Requested     Estimated               Clock   
Starting Clock     Frequency     Frequency     Period        Period        Slack     Type    
---------------------------------------------------------------------------------------------
cpu|clk            70.0 MHz      72.4 MHz      14.286        13.808        0.478     inferred
System             70.0 MHz      171.0 MHz     14.286        5.849         8.437     system  
=============================================================================================



Clock Relationships
*******************

Clocks             |    rise  to  rise   |    fall  to  fall    |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------
Starting  Ending   |  constraint  slack  |  constraint  slack   |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------
cpu|clk   cpu|clk  |  14.286      0.478  |  14.286      12.022  |  7.143       3.637  |  7.143       4.825
==========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port            Starting             User           Arrival     Required           
Name            Reference            Constraint     Time        Time         Slack 
                Clock                                                              
-----------------------------------------------------------------------------------
clk             NA                   NA             NA          NA           NA    
data_ex[0]      cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[1]      cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[2]      cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[3]      cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[4]      cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[5]      cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[6]      cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[7]      cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[8]      cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[9]      cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[10]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[11]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[12]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[13]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[14]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[15]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[16]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[17]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[18]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[19]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[20]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[21]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[22]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[23]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[24]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[25]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[26]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[27]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[28]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[29]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[30]     cpu|clk (rising)     NA             0.000       12.715       12.715
data_ex[31]     cpu|clk (rising)     NA             0.000       12.715       12.715
reset           System (rising)      NA             0.000       8.437        8.437 
===================================================================================


Output Ports: 

Port          Starting             User           Arrival     Required          
Name          Reference            Constraint     Time        Time         Slack
              Clock                                                             
--------------------------------------------------------------------------------
over_flow     cpu|clk (rising)     NA             12.635      14.286       1.651
================================================================================



====================================
Detailed Report for Clock: cpu|clk
====================================



Starting Points with worst slack 
********************************

                                                                         Arrival          
Instance                    Type     Pin     Net                         Time        Slack
                                                                                          
------------------------------------------------------------------------------------------
idex_out.ex_fast[6]         FDR      Q       idex_out.ex_iso[6]          1.837       0.478
exmem_out.alu_result[0]     FDR      Q       exmem_out.alu_result[0]     1.273       1.043
exmem_out.alu_result[1]     FDR      Q       exmem_out.alu_result[1]     1.273       1.043
idex_out.ex[6]              FDR      Q       idex_out.ex[6]              1.921       1.117
memwb_out.alu_result[0]     FDR      Q       memwb_out.alu_result[0]     1.178       1.137
memwb_out.alu_result[1]     FDR      Q       memwb_out.alu_result[1]     1.178       1.137
memwb_out.memdata[0]        FDR      Q       memwb_out.memdata[0]        1.178       1.137
memwb_out.memdata[1]        FDR      Q       memwb_out.memdata[1]        1.178       1.137
memwb_out.wb_fast[0]        FDR      Q       memwb_out.wb_fast[0]        1.178       1.137
idex_out.ex[5]              FDR      Q       idex_out.ex[5]              1.881       1.157
==========================================================================================


Ending Points with worst slack 
******************************

                                                                          Required          
Instance                     Type     Pin     Net                         Time         Slack
                                                                                            
--------------------------------------------------------------------------------------------
exmem_out.alu_result[5]      FDR      D       exmem_in.alu_result[5]      14.002       0.478
exmem_out.alu_result[27]     FDR      D       exmem_in.alu_result[27]     14.002       0.574
exmem_out.alu_result[0]      FDR      D       exmem_in.alu_result[0]      14.002       0.613
exmem_out.alu_result[3]      FDR      D       exmem_in.alu_result[3]      14.002       0.613
exmem_out.alu_result[24]     FDR      D       exmem_in.alu_result[24]     14.002       0.642
exmem_out.alu_result[7]      FDR      D       exmem_in.alu_result[7]      14.002       0.681
exmem_out.alu_result[8]      FDR      D       exmem_in.alu_result[8]      14.002       0.681
exmem_out.alu_result[9]      FDR      D       exmem_in.alu_result[9]      14.002       0.681
exmem_out.alu_result[10]     FDR      D       exmem_in.alu_result[10]     14.002       0.681
exmem_out.alu_result[11]     FDR      D       exmem_in.alu_result[11]     14.002       0.681
============================================================================================



Worst Paths Information
***********************


Path information for path number 1: 
    - Setup time:                         0.284
    = Required time:                      14.002

    - Propagation  time:                  13.524
    = Slack (critical) :                  0.478

    Starting point:                       idex_out.ex_fast[6] / Q
    Ending point:                         exmem_out.alu_result[5] / D
    The start point is clocked by         cpu|clk [rising] on pin C
    The end   point is clocked by         cpu|clk [rising] on pin C

Instance / Net                           Pin      Pin               Arrival     Fan
Name                           Type      Name     Dir     Delay     Time        Out
-----------------------------------------------------------------------------------
idex_out.ex_fast[6]            FDR       Q        Out     1.837     1.837          
idex_out.ex_iso[6]             Net                                              29 
U8.out1_1[0]                   LUT3      I2       In                1.837          
U8.out1_1[0]                   LUT3      O        Out     0.723     2.560          
out1_1[0]                      Net                                              1  
U8.out1_3[0]                   LUT4      I0       In                2.560          
U8.out1_3[0]                   LUT4      O        Out     0.791     3.351          
read21[0]                      Net                                              2  
G_10471                        LUT3      I0       In                3.351          
G_10471                        LUT3      O        Out     1.148     4.499          
G_10471                        Net                                              6  
U2.G_70                        LUT2      I0       In                4.499