coreofcpu.ta

几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码

U2.shiftin_22[28]            LUT3      O        Out     0.717     10.249         
shiftin_22[28]               Net                                              2  
U2.alu_out_0[27]             LUT3      I1       In                10.249         
U2.alu_out_0[27]             LUT3      O        Out     0.649     10.898         
N_29                         Net                                              1  
U2.alu_out_bm[27]            LUT3      I1       In                10.898         
U2.alu_out_bm[27]            LUT3      O        Out     0.649     11.547         
alu_out_bm[27]               Net                                              1  
U2.alu_out[27]               MUXF5     I1       In                11.547         
U2.alu_out[27]               MUXF5     O        Out     0.427     11.974         
alu_result[27]               Net                                              1  
exmem_out.alu_result[27]     FDR       D        In                11.974         
=================================================================================


Path information for path number 5: 
    Requested Period:                     13.333
    - Setup time:                         0.226
    = Required time:                      13.107

    - Propagation  time:                  11.968
    = Slack  :                            1.139

    Starting point:                       memwb_out.wb_0_rep1 / Q
    Ending point:                         exmem_out.alu_result[5] / D
    The start point is clocked by         cpu|clk [rising] on pin C
    The end   point is clocked by         cpu|clk [rising] on pin C

Instance / Net                        Pin      Pin               Arrival     Fan
Name                        Type      Name     Dir     Delay     Time        Out
--------------------------------------------------------------------------------
memwb_out.wb_0_rep1         FDR       Q        Out     1.131     1.131          
memwb_out.wb_0_rep1         Net                                              6  
U11.out1[3]                 LUT3      I2       In                1.131          
U11.out1[3]                 LUT3      O        Out     1.629     2.760          
memtoreg_out[3]             Net                                              25 
U8.out1_3[3]                LUT4      I2       In                2.760          
U8.out1_3[3]                LUT4      O        Out     0.717     3.477          
read21[3]                   Net                                              2  
G_10474                     LUT3      I0       In                3.477          
G_10474                     LUT3      O        Out     1.169     4.645          
G_10474                     Net                                              9  
U2.G_74                     LUT3      I0       In                4.645          
U2.G_74                     LUT3      O        Out     1.074     5.720          
un6_shiftcnt_c4             Net                                              6  
U2.shiftcnt_3_1_fast[4]     LUT3      I2       In                5.720          
U2.shiftcnt_3_1_fast[4]     LUT3      O        Out     1.074     6.794          
shiftcnt_3_1_fast[4]        Net                                              6  
U2.shiftin_13[11]           MUXF5     S        In                6.794          
U2.shiftin_13[11]           MUXF5     O        Out     1.200     7.994          
shiftin_13[11]              Net                                              2  
U2.shiftin_16[11]           LUT3      I0       In                7.994          
U2.shiftin_16[11]           LUT3      O        Out     0.717     8.710          
shiftin_16[11]              Net                                              2  
U2.shiftin_19[7]            LUT3      I1       In                8.710          
U2.shiftin_19[7]            LUT3      O        Out     0.817     9.527          
shiftin_19[7]               Net                                              3  
U2.shiftin_22[5]            LUT3      I1       In                9.527          
U2.shiftin_22[5]            LUT3      O        Out     0.717     10.244         
shiftin_22[5]               Net                                              2  
U2.alu_out_0[5]             LUT3      I0       In                10.244         
U2.alu_out_0[5]             LUT3      O        Out     0.649     10.893         
alu_out_0[5]                Net                                              1  
U2.alu_out_bm[5]            LUT3      I2       In                10.893         
U2.alu_out_bm[5]            LUT3      O        Out     0.649     11.542         
alu_out_bm[5]               Net                                              1  
U2.alu_out[5]               MUXF5     I1       In                11.542         
U2.alu_out[5]               MUXF5     O        Out     0.427     11.968         
alu_result[5]               Net                                              1  
exmem_out.alu_result[5]     FDR       D        In                11.968         
================================================================================



##### END TIMING REPORT #####

Writing Analyst data base D:\My Documents\New Folder (4)\rev_1\coreofCPU_ta.srm
Mapper successful!
Process took 19.158 seconds realtime, 19.788 seconds cputime