coreofcpu.ta

几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码

U8.out1_3[2]                LUT4      I2       In                2.760          
U8.out1_3[2]                LUT4      O        Out     0.817     3.576          
read21[2]                   Net                                              3  
G_10473                     LUT3      I0       In                3.576          
G_10473                     LUT3      O        Out     1.074     4.651          
N_12192                     Net                                              6  
U2.G_74                     LUT3      I2       In                4.651          
U2.G_74                     LUT3      O        Out     1.074     5.725          
un6_shiftcnt_c4             Net                                              6  
U2.shiftcnt_3_1_fast[4]     LUT3      I2       In                5.725          
U2.shiftcnt_3_1_fast[4]     LUT3      O        Out     1.074     6.799          
shiftcnt_3_1_fast[4]        Net                                              6  
U2.shiftin_13[11]           MUXF5     S        In                6.799          
U2.shiftin_13[11]           MUXF5     O        Out     1.200     7.999          
shiftin_13[11]              Net                                              2  
U2.shiftin_16[11]           LUT3      I0       In                7.999          
U2.shiftin_16[11]           LUT3      O        Out     0.717     8.716          
shiftin_16[11]              Net                                              2  
U2.shiftin_19[7]            LUT3      I1       In                8.716          
U2.shiftin_19[7]            LUT3      O        Out     0.817     9.532          
shiftin_19[7]               Net                                              3  
U2.shiftin_22[5]            LUT3      I1       In                9.532          
U2.shiftin_22[5]            LUT3      O        Out     0.717     10.249         
shiftin_22[5]               Net                                              2  
U2.alu_out_0[5]             LUT3      I0       In                10.249         
U2.alu_out_0[5]             LUT3      O        Out     0.649     10.898         
alu_out_0[5]                Net                                              1  
U2.alu_out_bm[5]            LUT3      I2       In                10.898         
U2.alu_out_bm[5]            LUT3      O        Out     0.649     11.547         
alu_out_bm[5]               Net                                              1  
U2.alu_out[5]               MUXF5     I1       In                11.547         
U2.alu_out[5]               MUXF5     O        Out     0.427     11.974         
alu_result[5]               Net                                              1  
exmem_out.alu_result[5]     FDR       D        In                11.974         
================================================================================


Path information for path number 4: 
    Requested Period:                     13.333
    - Setup time:                         0.226
    = Required time:                      13.107

    - Propagation  time:                  11.974
    = Slack  :                            1.134

    Starting point:                       memwb_out.wb_0_rep1 / Q
    Ending point:                         exmem_out.alu_result[27] / D
    The start point is clocked by         cpu|clk [rising] on pin C
    The end   point is clocked by         cpu|clk [rising] on pin C

Instance / Net                         Pin      Pin               Arrival     Fan
Name                         Type      Name     Dir     Delay     Time        Out
---------------------------------------------------------------------------------
memwb_out.wb_0_rep1          FDR       Q        Out     1.131     1.131          
memwb_out.wb_0_rep1          Net                                              6  
U11.out1[2]                  LUT3      I2       In                1.131          
U11.out1[2]                  LUT3      O        Out     1.629     2.760          
memtoreg_out[2]              Net                                              25 
U8.out1_3[2]                 LUT4      I2       In                2.760          
U8.out1_3[2]                 LUT4      O        Out     0.817     3.576          
read21[2]                    Net                                              3  
G_10473                      LUT3      I0       In                3.576          
G_10473                      LUT3      O        Out     1.074     4.651          
N_12192                      Net                                              6  
U2.G_74                      LUT3      I2       In                4.651          
U2.G_74                      LUT3      O        Out     1.074     5.725          
un6_shiftcnt_c4              Net                                              6  
U2.shiftcnt_3_1_fast[4]      LUT3      I2       In                5.725          
U2.shiftcnt_3_1_fast[4]      LUT3      O        Out     1.074     6.799          
shiftcnt_3_1_fast[4]         Net                                              6  
U2.shiftin_13[36]            MUXF5     S        In                6.799          
U2.shiftin_13[36]            MUXF5     O        Out     1.200     7.999          
shiftin_13[36]               Net                                              2  
U2.shiftin_16[28]            LUT3      I1       In                7.999          
U2.shiftin_16[28]            LUT3      O        Out     0.817     8.816          
shiftin_16[28]               Net                                              3  
U2.shiftin_19[28]            LUT3      I0       In                8.816          
U2.shiftin_19[28]            LUT3      O        Out     0.717     9.532          
shiftin_19[28]               Net                                              2  
U2.shiftin_22[28]            LUT3      I0       In                9.532