traplog.tlg

来自「几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码」· TLG 代码 · 共 40 行

Synthesizing work.top.gen
Synthesizing work.ram_r_w.select_ram
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
Synthesizing virtex2.ram32x1d.syn_black_box
Post processing for virtex2.ram32x1d.syn_black_box
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
@W:"syng0a00432":1829:12:1829:17|Port spo of entity virtex2.ram32x1d is unconnected
Post processing for work.ram_r_w.select_ram
@W:"syng0a00432":32:2:32:5|Input oclk is unused
Post processing for work.top.gen