cpu.prj

几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码

#-- Synplicity, Inc.
#-- Version 7.2        
#-- Project file D:\My Documents\New Folder (4)\CPU.prj
#-- Written on Sun Jun 15 16:45:39 2003


#add_file options
add_file -vhdl -lib work "control.vhd"
add_file -vhdl -lib work "data_rom.vhd"
add_file -vhdl -lib work "mux2_1.vhd"
add_file -vhdl -lib work "mux4_1.vhd"
add_file -vhdl -lib work "opt.vhd"
add_file -vhdl -lib work "alu.vhd"
add_file -vhdl -lib work "ins_rom.vhd"
add_file -vhdl -lib work "coreofCPU.vhd"


#implementation: "rev_1"
impl -add rev_1

#device options
set_option -technology VIRTEX2P
set_option -part XC2VP2
set_option -package FF672
set_option -speed_grade -7

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -use_fsm_explorer 0

#map options
set_option -frequency 75.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -modular 0
set_option -retiming 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/coreofCPU.edf"

#implementation attributes
set_option -vlog_std v2001
set_option -compiler_compatible ""
impl -active "rev_1"