data_rom.vhd

几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码

--core_design
--data memory ram
--all right reserved
--(2147483647+1)*2)
--or (clk'event and clk='0' and ras='1') 
--clk='1' and 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity dram is
  generic (ram_delay:time:=3 ns);
  port (clk:in std_logic;
	addr:in std_logic_vector(31 downto 0);
        data_in:in std_logic_vector(31 downto 0);
        data_out:out std_logic_vector(31 downto 0);
	ras:in std_logic;
	we:in std_logic
       );
end dram;

architecture sl of dram is
  constant dram_high:integer:=30;
  subtype dram_range is integer range 0 to dram_high;
  subtype memory_data is std_logic_vector(31 downto 0);
  type memory is array (dram_range) of memory_data;
  signal dram_array:memory;

function logic2int(din:std_logic_vector(31 downto 0)) return dram_range is
    variable result:dram_range:=0;
  begin
    for i in 0 to 31 loop 
      if din(i)='1' then
        result:=result+(2**i);
      end if;
    end loop;
    return result;
end logic2int;

begin
  process(clk)
   variable address:natural;
   begin
    if clk'event and clk='0' then
     if ras='1' then
        address:=conv_integer(addr);
        data_out<=dram_array(address) after ram_delay;
       elsif we='1' then
        address:=conv_integer(addr);
        dram_array(address)<=data_in after ram_delay;
       else 
        data_out <=(others=>'Z');
       end if;
    end if;  
  end process;
end sl;
      

--process(clk)
 --  variable address:natural;
--   begin
--    if (ras='1') then
 --     address:=conv_integer(addr);
 --     data_out<=dram_array(address) after ram_delay;
--    elsif (clk='1' and we='1') then
   --   address:=conv_integer(addr);
   --   dram_array(address)<=data_in after ram_delay;
 --   else 
  --    data_out <=(others=>'Z');
 --   end if;
 -- end process;