ddr_sdram.vhd

用VHDL编写DDR SDRAM Controller的源代码

    signal    cm_ack	:    std_logic;                
                             
    signal    CLK100    :    std_logic;                    
    signal    CLK200    :    std_logic; 
    signal    clklocked :    std_logic;
    signal    dqoe1     :    std_logic;                    
    signal    dqoe2     :    std_logic;                    
    signal    dqoe3     :    std_logic;                    
    signal    dqoe4     :    std_logic;                    

begin

 
	-- instantiate the control interface module
    control1 : ddr_control_interface
         generic map (
              ASIZE => ASIZE
         )
         port map  (
	          CLK       => CLK100,
	          RESET_N   => RESET_N,
	          CMD       => CMD,
	          ADDR      => ADDR,
	          REF_ACK   => ref_ack,
	          CM_ACK    => cm_ack,
	          NOP       => nop,
	          READA     => reada,
	          WRITEA    => writea,
	          REFRESH   => refresh,
	          PRECHARGE => precharge,
	          LOAD_MODE => load_mode,
	          SADDR     => saddr,
	          SC_CL     => sc_cl,
	          SC_RC     => sc_rc,
	          SC_RRD    => sc_rrd,
	          SC_PM     => sc_pm,
	          SC_BL     => sc_bl,
	          REF_REQ   => ref_req,
	          CMD_ACK   => CMDACK
         );
	                
	                
    -- instantiate the command module
    command1 : ddr_command
         generic map(
              ASIZE     => ASIZE, 		
              DSIZE     => DSIZE, 		
              ROWSIZE   => ROWSIZE, 	
              COLSIZE   => COLSIZE, 	
              BANKSIZE  => BANKSIZE, 
              ROWSTART  => ROWSTART, 
              COLSTART  => COLSTART, 
              BANKSTART => BANKSTART
         )
         port map  (
	          CLK       => CLK100,
	          RESET_N   => RESET_N,
	          SADDR     => saddr,
	          NOP       => nop,
	          READA     => reada,
	          WRITEA    => writea,
	          REFRESH   => refresh,
	          PRECHARGE => precharge,
	          LOAD_MODE => load_mode,
	          SC_CL     => sc_cl,
	          SC_RC     => sc_rc,
	          SC_RRD    => sc_rrd,
	          SC_PM     => sc_pm,
	          SC_BL     => sc_bl,
	          REF_REQ   => ref_req,
	          REF_ACK   => ref_ack,
	          CM_ACK    => cm_ack,
	          OE        => oe,
	          SA        => ISA,
	          BA        => IBA,
	          CS_N      => ICS_N,
	          CKE       => ICKE,
	          RAS_N     => IRAS_N,
	          CAS_N     => ICAS_N,
	          WE_N      => IWE_N
         );
	    
	                
    -- instantiate the data path module
    data_path1 : ddr_data_path 
         port map  (
	          CLK100    => CLK100,
              CLK200    => CLK200,
	          RESET_N   => RESET_N,
	          OE        => oe,
	          DATAIN    => DATAIN(31 downto 0),
	          DM        => DM(3 downto 0),
	          DATAOUT   => DATAOUT(31 downto 0),
              DQIN      => DQIN(15 downto 0),
              DQOUT     => DQOUT(15 downto 0),
	          DQM       => DQM(1 downto 0),
              DQS       => DQS(1 downto 0),
              SC_CL     => sc_cl,
              DQOE      => dqoe1
	    );

    data_path2 : ddr_data_path 
         port map  (
	          CLK100    => CLK100,
              CLK200    => CLK200,
	          RESET_N   => RESET_N,
	          OE        => oe,
	          DATAIN    => DATAIN(63 downto 32),
	          DM        => DM(7 downto 4),
	          DATAOUT   => DATAOUT(63 downto 32),
              DQIN      => DQIN(31 downto 16),
              DQOUT     => DQOUT(31 downto 16),
	          DQM       => DQM(3 downto 2),
              DQS       => DQS(3 downto 2),
              SC_CL     => sc_cl,
              DQOE      => dqoe2
	    );

    data_path3 : ddr_data_path 
         port map  (
	          CLK100    => CLK100,
              CLK200    => CLK200,
	          RESET_N   => RESET_N,
	          OE        => oe,
	          DATAIN    => DATAIN(95 downto 64),
	          DM        => DM(11 downto 8),
	          DATAOUT   => DATAOUT(95 downto 64),
              DQIN      => DQIN(47 downto 32),
              DQOUT     => DQOUT(47 downto 32),
	          DQM       => DQM(5 downto 4),
              DQS       => DQS(5 downto 4),
              SC_CL     => sc_cl,
              DQOE      => dqoe3
	    );

    data_path4 : ddr_data_path 
         port map  (
	          CLK100    => CLK100,
              CLK200    => CLK200,
	          RESET_N   => RESET_N,
	          OE        => oe,
	          DATAIN    => DATAIN(127 downto 96),
	          DM        => DM(15 downto 12),
	          DATAOUT   => DATAOUT(127 downto 96),
              DQIN      => DQIN(63 downto 48),
              DQOUT     => DQOUT(63 downto 48),
	          DQM       => DQM(7 downto 6),
              DQS       => DQS(7 downto 6),
              SC_CL     => sc_cl,
              DQOE      => dqoe4
	    );
	    
    pll : pll1
         port map (
              inclock => CLK,
              locked  => clklocked,
              clock0  => CLK100,
              clock1  => CLK200
         );
              
	    
    -- Add a level flops to the sdram i/o that can be place
    -- by the router into the I/O cells
    process(CLK100)
    begin
         if rising_edge(CLK100) then
              SA        <= ISA;
              BA        <= IBA;
              CS_N      <= ICS_N;
              CKE       <= ICKE;
              RAS_N     <= IRAS_N;
              CAS_N     <= ICAS_N;
              WE_N      <= IWE_N;
         end if;
    end process;

-- capture the read data
    process(CLK200, RESET_N)
    begin
         if (RESET_N = '0') then
              DQIN <= (others => '0');
         elsif (falling_edge(CLK200)) then
              DQIN <= DQ;
         end if;
    end process;
    
    
    -- tri-state the data bus using the OE signal from the main controller.
	
DQ(15 downto 0) <= DQOUT(15 downto 0) when dqoe1 = '1' else (others => 'Z');
DQ(31 downto 16) <= DQOUT(31 downto 16) when dqoe2 = '1' else (others => 'Z');
DQ(47 downto 32) <= DQOUT(47 downto 32) when dqoe3 = '1' else (others => 'Z');
DQ(63 downto 48) <= DQOUT(63 downto 48) when dqoe4 = '1' else (others => 'Z');


end RTL;