📄 ddr_sdram_tb.vhd
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addr(12 downto 9) <= "0100";
end if;
cmd <= "110";
wait until (cmdack = '1'); -- Wait for the controller to ack the command
wait until (CLK'event and CLK = '1');
wait for 1 ns;
cmd <= "000"; -- Clear the command by issuing a NOP
end config;
begin
-- The SDRAM Controller
ddr: ddr_sdram
port map (
CLK => clk,
RESET_N => reset_n,
ADDR => addr,
CMD => cmd,
CMDACK => cmdack,
DATAIN => datain,
DATAOUT => dataout,
DM => dm,
SA => sa,
BA => ba,
CS_N => cs_n,
CKE => cke,
RAS_N => ras_n,
CAS_N => cas_n,
WE_N => we_n,
DQ => dq,
DQM => dqm,
DQS => dqs
);
-- The SDRAMs
B000: mt46v4m16
port map(
Dq => dq(15 downto 0),
Dqs => dqs(1 downto 0),
Addr => sa(11 downto 0),
Ba => ba,
Clk => clk2,
Clk_n => clk2n,
Cke => cke,
Cs_n => cs_n(0),
Cas_n => cas_n,
Ras_n => ras_n,
We_n => we_n,
Dm => dqm(1 downto 0)
);
B001: mt46v4m16
port map(
Dq => dq(31 downto 16),
Dqs => dqs(3 downto 2),
Addr => sa(11 downto 0),
Ba => ba,
Clk => clk2,
Clk_n => clk2n,
Cke => cke,
Cs_n => cs_n(0),
Cas_n => cas_n,
Ras_n => ras_n,
We_n => we_n,
Dm => dqm(3 downto 2)
);
B010: mt46v4m16
port map(
Dq => dq(47 downto 32),
Dqs => dqs(5 downto 4),
Addr => sa(11 downto 0),
Ba => ba,
Clk => clk2,
Clk_n => clk2n,
Cke => cke,
Cs_n => cs_n(0),
Cas_n => cas_n,
Ras_n => ras_n,
We_n => we_n,
Dm => dqm(5 downto 4)
);
B011: mt46v4m16
port map(
Dq => dq(63 downto 48),
Dqs => dqs(7 downto 6),
Addr => sa(11 downto 0),
Ba => ba,
Clk => clk2,
Clk_n => clk2n,
Cke => cke,
Cs_n => cs_n(0),
Cas_n => cas_n,
Ras_n => ras_n,
We_n => we_n,
Dm => dqm(7 downto 6)
);
B100: mt46v4m16
port map(
Dq => dq(15 downto 0),
Dqs => dqs(1 downto 0),
Addr => sa(11 downto 0),
Ba => ba,
Clk => clk2,
Clk_n => clk2n,
Cke => cke,
Cs_n => cs_n(1),
Cas_n => cas_n,
Ras_n => ras_n,
We_n => we_n,
Dm => dqm(1 downto 0)
);
B101: mt46v4m16
port map(
Dq => dq(31 downto 16),
Dqs => dqs(3 downto 2),
Addr => sa(11 downto 0),
Ba => ba,
Clk => clk2,
Clk_n => clk2n,
Cke => cke,
Cs_n => cs_n(1),
Cas_n => cas_n,
Ras_n => ras_n,
We_n => we_n,
Dm => dqm(3 downto 2)
);
B110: mt46v4m16
port map(
Dq => dq(47 downto 32),
Dqs => dqs(5 downto 4),
Addr => sa(11 downto 0),
Ba => ba,
Clk => clk2,
Clk_n => clk2n,
Cke => cke,
Cs_n => cs_n(1),
Cas_n => cas_n,
Ras_n => ras_n,
We_n => we_n,
Dm => dqm(5 downto 4)
);
B111: mt46v4m16
port map(
Dq => dq(63 downto 48),
Dqs => dqs(7 downto 6),
Addr => sa(11 downto 0),
Ba => ba,
Clk => clk2,
Clk_n => clk2n,
Cke => cke,
Cs_n => cs_n(1),
Cas_n => cas_n,
Ras_n => ras_n,
We_n => we_n,
Dm => dqm(7 downto 6)
);
-- Generate the clocks
process
begin
clk <= '0';
wait for 5000 ps;
clk <= '1';
wait for 5000 ps;
end process;
process
begin
clk2 <= '0';
clk2n <= '1';
wait for 3000 ps;
clk2 <= '1';
clk2n <= '0';
wait for 5000 ps;
clk2 <= '0';
clk2n <= '1';
wait for 2000 ps;
end process;
process
variable x : integer := 0;
variable j : integer := 0;
variable yi : integer := 0;
variable bl : integer := 0;
variable zi : integer := 0;
begin
reset_n <= '0';
wait for 100 ns;
reset_n <= '1';
wait for 200 ns;
report "Testing data mask inputs";
config("010", "10", 8, '0', x"05F6", addr, cmdack, cmd);
wait for 1000 ns;
report "writing pattern 0,1,2,3,4,5,6,7 to sdram at address 0x0";
burst_write(x"00000000000000000000000000000000", x"000000", 4, 2, x"0000", addr, datain, dm, cmdack, cmd);
wait for 1000 ns;
report "Reading and verifing the pattern 0,1,2,3,4,5,6,7 at sdram address 0x0";
burst_read(x"00000000000000000000000000000000", x"000000", 4, 2, 2, addr, dataout, cmdack, cmd);
wait for 1000 ns;
report "Writing pattern 0xfffffff0, 0xfffffff1, 0xfffffff2, 0xfffffff3, 0xfffffff4, 0xfffffff5, 0xfffffff6, 0xfffffff7";
report "with DM set to 0xf";
burst_write(x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0", x"000000", 4, 2, x"ffff", addr, datain, dm, cmdack, cmd);
wait for 1000 ns;
report "Reading and verifing that the pattern at sdram address 0x0 is";
report "still 0,1,2,3,4,5,6,7";
burst_read(x"00000000000000000000000000000000", x"000000", 4, 2, 2, addr, dataout, cmdack, cmd);
wait for 1000 ns;
report "End of data mask test";
report "running data pattern tests";
bl := 2;
for x in 1 to 3 loop -- step through the four burst lengths 2,4,8
y <= "010";
for yi in 2 to 3 loop
z <= "10";
for zi in 2 to 3 loop
config(y, z, bl, '0', x"05F6", addr, cmdack, cmd);
-- perform 1024 burst writes to the first chip select, writing a ramp pattern
report "Peforming burst write to first sdram bank";
test_data <= (others => '0');
test_addr <= (others => '0');
for j in 0 to 1024 loop
burst_write(test_data, test_addr, bl/2, zi, x"0000", addr, datain, dm, cmdack, cmd);
test_data <= test_data + bl;
test_addr <= test_addr + bl;
wait for 100 ns;
end loop;
-- perform 1024 burst reads to the first chip select, verifing the ramp pattern
report "Performing burst read, verify ramp values in first sdram bank";
test_data <= (others => '0');
test_addr <= (others => '0');
for j in 0 to 1024 loop
burst_read(test_data, test_addr, bl/2, yi, zi, addr, dataout, cmdack, cmd);
test_data <= test_data + bl;
test_addr <= test_addr + bl;
end loop;
wait for 500 ns;
-- perform 1024 burst writes to the second chip select, writing a ramp pattern
report "Peforming burst write to second sdram bank";
test_data <= x"00000000000000000000000000400000";
test_addr <= "1000000000000000000000";
for j in 0 to 1024 loop
burst_write(test_data, test_addr, bl/2, zi, x"0000", addr, datain, dm, cmdack, cmd);
test_data <= test_data + bl;
test_addr <= test_addr + bl;
wait for 100 ns;
end loop;
-- perform 1024 burst reads to the second chip select, verifing the ramp pattern
report "Performing burst read, verify ramp values in second sdram bank";
test_data <= x"00000000000000000000000000400000";
test_addr <= "1000000000000000000000";
for j in 0 to 1024 loop
burst_read(test_data, test_addr, bl/2, yi, zi, addr, dataout, cmdack, cmd);
test_data <= test_data + bl;
test_addr <= test_addr + bl;
end loop;
wait for 5000 ns;
report "Test complete";
z <= z+1;
end loop;
y<=y+1;
end loop;
bl := bl * 2;
end loop;
assert false report "all tests complete" severity failure;
end process;
end rtl;
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