apex20ke_mf.vhd

用VHDL编写DDR SDRAM Controller的源代码

      if wren_rgd'event and wren_rgd = '0' and write_incomplete = '1' then
        assert false
           report "Insufficient write cycle time, write failed! "
           severity warning;
      elsif pattern_int'event and write_incomplete = '1' then
        assert false
           report "Insufficient pattern hold time, write failed! "
           severity warning;
      elsif wraddress_rgd'event and write_incomplete = '1' then
        assert false
           report "Insufficient address hold time, write failed! "
           severity warning;
      elsif wrdelete_delayed'event and wrdelete_delayed = '0' and 
            write_incomplete = '1' then
        assert false
           report "Insufficient delete cycle time, delete failed! "
           severity warning;
      elsif wrdelete'event and wrdelete = '1' and 
           write_incomplete = '1' then
        assert false
           report "Insufficient write cycle time, write failed! "
           severity warning;
      elsif wrxused_int'event and write_incomplete = '1' and 
            wrdelete = '0' then
        assert false
           report "wrxused signal changed during write! "
           severity warning;
      elsif mstart_rgd1'event and write_incomplete = '1' and 
            mstart_rgd1 = '1' then
        assert false
           report "Incorrect read attempt during write! "
           severity warning;
      end if;
   if pattern_int'event then
      if rdbusy_delayed = '1' then
        assert false
           report "Insufficient read time, read failed! "
           severity warning;
      elsif rdbusy_delayed = '0' and mnext = '1' then
        assert false
           report "Illegal pattern change during read, read failed! "
           severity warning;
      end if;
   end if;
  
end process msg;

-- Evaluate parameters
pattern_int <= pattern when pattern_reg = "UNREGISTERED" else pattern_rgd;
wrx_int     <= wrx when wrx_reg = "UNREGISTERED" else wrx_rgd;
wrxused_int <= wrxused when wrx_reg = "UNREGISTERED" else wrxused_rgd;
maddress    <= maddress_int when output_reg = "UNREGISTERED" else maddress_rgd;
mbits       <= mbits_int when output_reg = "UNREGISTERED" else mbits_rgd;
mfound      <= mfound_int when output_reg = "UNREGISTERED" else mfound_rgd;
mcount      <= mcount_int when output_reg = "UNREGISTERED" else mcount_rgd;
wrbusy      <= wrbusy_int;
rdbusy      <= rdbusy_int;
outclock_int <= outclock when output_reg = "OUTCLOCK" else inclock;
outaclr_int  <= outaclr when output_reg = "OUTCLOCK" else inaclr;

-- Generate write clock
write_clock <= (not inclock) and wren_rgd;
wrdelete_delayed <= wrdelete after 2 ns;
rdbusy_delayed <= rdbusy_int after 2 ns;

-- Evaluate registered signals
inputreg: process (inaclr, inclock)

    variable count : natural := 0;
    variable index : natural :=0;
    variable next_search : natural := 0;

begin
   if inaclr = '1' then
	   if pattern_aclr = "ON" then 
         pattern_rgd <= (others => '0'); 
      end if;
	   if wrx_aclr = "ON" then 
         wrx_rgd <= (others => '0'); 
	      wrxused_rgd <= '0';
      end if;
	   if wraddress_aclr = "ON" then 
         wraddress_rgd <= (others => '0'); 
      end if;
	   if wrcontrol_aclr = "ON" then 
         wren_rgd <= '0'; 
      end if;
	elsif inclock'event and inclock = '1' and inclocken = '1' then
      pattern_rgd <= pattern;
      wrx_rgd <= wrx;
      wrxused_rgd <= wrxused;
      wraddress_rgd <= wraddress;
      wren_rgd <= wren;
      write_start_rgd <= write_start;
      write_incomplete <= wrbusy_int;
 
-- read
     if wren_rgd = '0' then
	   if first_read_clock = true or match_mode = "SINGLE" then 
         count := 0; 
         index := 0;
         next_search := 0;
         second_read_clock <= true;
         next_read_clock <= false;
   --    mfound_int <= '0'; -- Force mfound to 0 when count is 0.
         mbits_int <= (others => '0');
      end if;
	   if match_mode = "SINGLE" or match_mode = "FASTMULTIPLE" or 
         second_read_clock = true or get_next_match = '1' then
         second_read_clock <= false;
      if get_next_match = '1' then 
         index := next_search; 
      end if;
      maddr: for i in index to 2**widthad -1 loop
          if get_next_match = '1' and next_search = 2**widthad then
		       mfound_int <= '0';
		       exit maddr;
	       end if;
        mword:    for j in 0 to width-1 loop
		    if (((x_array(i)(j) = '0') and 
             (cam_array(i)(j) = pattern_int(j))) or 
             ((x_array(i)(j) = '1') and 
             (cam_array(i)(j) = '0'))) then 
		       if j = width-1 then 
		          mfound_int <= '1';
		          count := count + 1;
                mbits_int(i) <= '1';
                maddress_int <= 
                ieee.std_logic_arith.conv_std_logic_vector(i, widthad);
                if i < 2**widthad  then
                   next_search := i+1;
		             next_read_clock <= true;
                end if;
		          exit maddr;
		       end if;
		    else 
             exit mword;
          end if;
	     end loop mword;
        if (i = (2 **widthad) -1) and count = 0 then
          mfound_int <= '0'; 
        end if;
	   end loop maddr;
	   end if;
      mcount_int <= 
      ieee.std_logic_arith.conv_std_logic_vector(count, widthad);
   end if;
   end if; -- read
end process inputreg;

outputreg: process (outaclr_int, outclock_int)
begin
  if output_reg = "OUTCLOCK" or output_reg = "INCLOCK" then
    if outaclr_int = '1' then
       if output_aclr = "ON" then 
          maddress_rgd <= (others => '0');
	  mbits_rgd <= (others => '0');
	  mfound_rgd <= '0';
	  mcount_rgd <= (others => '0');
       end if;
    elsif outclock_int'event and outclock_int = '1' and outclocken = '1' then
         mstart_rgd1 <= mstart;
         mstart_rgd2 <= mstart_rgd1;
         maddress_rgd <= maddress_int;
         mbits_rgd <= mbits_int;
         mfound_rgd <= mfound_int;
         mcount_rgd <= mcount_int;
    end if;
  end if;
end process outputreg;

write_busy_control: process(wren_rgd, wraddress_rgd, write_start_rgd) 
begin
   if wren_rgd'event and wren_rgd = '1' then 
      wrbusy_int <= '1' ;
   elsif wraddress_rgd'event and wren_rgd = '1' then
      wrbusy_int <= '1' ;
   elsif write_start_rgd'event and write_start_rgd = '1' then
      wrbusy_int <= '0' ;
   end if;
end process write_busy_control;

write_control: process(write0_done, write1_done, writex_done, wrbusy_int)
begin
   if wrbusy_int'event and wrbusy_int = '1' then
      write0 <= true;
   elsif wrbusy_int'event and wrbusy_int = '0' then 
      write0 <= false;
   elsif write0_done'event and write0_done = true then
      write1 <= true;
   elsif write1_done'event and write1_done = true then
      if wrxused_int = '1' then
         writex <= true;
      else 
         writex <= false;
      end if;
      write1 <= false;
   elsif writex_done'event and writex_done = true then
      write1 <= false;
      writex <= false;
   end if;
end process write_control;

write: process(write_clock, wrdelete, pattern_int, wrx_int, wraddress_rgd)
begin
   if cam_init = 1  then	
      if lpm_file = "UNUSED" then
         for i in 0 to (2**widthad)-1 loop
            cam_array(i) <= (others => '1');
            x_array(i) <= (others => '1');
         end loop;
      elsif lpm_filex = "UNUSED" then
	      cam_array <= hex_to_stdlogicarray(lpm_file);
         for i in 0 to (2**widthad)-1 loop
	         x_array(i) <= (others => '0');
         end loop;
      else
         cam_array <= hex_to_stdlogicarray(lpm_file);
         x_array <= hex_to_stdlogicarray(lpm_filex);
      end if;
   end if;
   cam_init <= 0;

   if write_clock = '1' then
     if wrdelete = '0' then
        if wrxused_int = '1' then
--write_zeros:
 	        if write0 = true then
              for i in 0 to width -1 loop
                 if pattern_int(i) = '0' then
            cam_array(ieee.std_logic_unsigned.conv_integer(wraddress_rgd))(i)
                    <= '0';
            x_array(ieee.std_logic_unsigned.conv_integer(wraddress_rgd))(i)
                    <= '0';
                 end if;
              end loop;
              write0_done <= true;
              write1_done <= false;
              writex_done <= false;
  	     end if;

--write_ones:
 	     if write1 = true then
           for i in 0 to width -1 loop
              if pattern_int(i) = '1' then
            cam_array(ieee.std_logic_unsigned.conv_integer(wraddress_rgd))(i)
                 <= '1';
            x_array(ieee.std_logic_unsigned.conv_integer(wraddress_rgd))(i)
                 <= '0';
              end if;
           end loop;
           write1_done <= true;
           write0_done <= false;
           writex_done <= false;
  	     end if;

--write_x:
 	     if writex = true then
           for i in 0 to width -1 loop
         x_array(ieee.std_logic_unsigned.conv_integer(wraddress_rgd))(i)
              <= wrx_int(i);
              if pattern_int(i) = '1' and wrx_int(i) = '1' then
            cam_array(ieee.std_logic_unsigned.conv_integer(wraddress_rgd))(i)
                 <= '0';
              end if;
           end loop;
           writex_done <= true;
           write0_done <= false;
           write1_done <= false;
  	     end if;
        if wrbusy_int = '1' then
           write_start_1 <= '1';
           write_start <= write_start_1;
        else
           write_start_1 <= '0';
           write_start <= '0';
        end if;
     else
--write_zeros:
 	     if write0 = true then
           for i in 0 to width -1 loop
              if pattern_int(i) = '0' then
            cam_array(ieee.std_logic_unsigned.conv_integer(wraddress_rgd))(i)
                 <= '0';
            x_array(ieee.std_logic_unsigned.conv_integer(wraddress_rgd))(i)
                 <= '0';
              end if;
           end loop;
           write0_done <= true;
           write1_done <= false;
           writex_done <= false;
  	     end if;

--write_ones:
 	     if write1 = true then
           for i in 0 to width -1 loop
              if pattern_int(i) = '1' then
            cam_array(ieee.std_logic_unsigned.conv_integer(wraddress_rgd))(i)
                 <= '1';
            x_array(ieee.std_logic_unsigned.conv_integer(wraddress_rgd))(i)
                 <= '0';
              end if;
           end loop;
           write1_done <= true;
           write0_done <= false;
           writex_done <= false;
  	     end if;

        if wrbusy_int = '1' then
           write_start <= '1';
        else
           write_start <= '0';
        end if;
     end if;
     else
--write_ones:
        for i in 0 to width -1 loop
         cam_array(ieee.std_logic_unsigned.conv_integer(wraddress_rgd))(i)
             <= '1';
        end loop;
        write1_done <= true;
        write0_done <= false;
        writex_done <= false;

--write_x:
 	     if writex = true then
           for i in 0 to width -1 loop
         x_array(ieee.std_logic_unsigned.conv_integer(wraddress_rgd))(i)
              <= '1';
           end loop;
           writex_done <= true;
           write0_done <= false;
           write1_done <= false;
  	     end if;
        if wrbusy_int = '1' then
           write_start <= '1';
        else
           write_start <= '0';
        end if;
     end if;
   end if;
end process write;

read_control: process(mstart, mstart_rgd1, mstart_rgd2, mnext)
begin
    if mstart'event and mstart = '1' then
	     first_read_clock <= true;
    elsif mstart_rgd1'event and mstart_rgd1 = '1' then
	     first_read_clock <= false;
        if match_mode = "SINGLE" or match_mode = "FASTMULTIPLE" then
           rdbusy_int <= '0' ;
	else
	   rdbusy_int <= '1';  -- must be "MULTIPLE" mode
        end if;
    elsif mstart_rgd2'event and mstart_rgd2 = '1' then
           rdbusy_int <= '0'; 
    end if;
    if mnext'event  and mnext = '1' and next_read_clock = true then
        get_next_match <= '1';
    elsif mnext'event and mnext = '0' then
        get_next_match <= '0';
    end if;
end process read_control;

end;






-- altclklock megafunction 
-- Restrictions: 
--   1. NORMAL operation mode only 
--   2. Zero delay outputs
--   3. Locked output remains high for the entire simulation time 
--      after it is locked, and goes low when inclocken is deasserted.
--      invalid_lock_cycles parameter is not used for behavioral simulation
--
library ieee;
use ieee.std_logic_1164.all;

entity altclklock is
   generic (
            inclock_period : natural;
            inclock_settings : string := "UNUSED";
            valid_lock_cycles : natural := 3;
            invalid_lock_cycles : natural := 3;
            valid_lock_multiplier : natural := 1;
            invalid_lock_multiplier : natural := 1;
            operation_mode : string := "NORMAL";
            clock0_boost : natural := 1;
            clock0_divide : natural := 1;
            clock1_boost : natural := 1;
            clock1_divide : natural := 1;
            clock0_settings : string := "UNUSED";
            clock1_settings : string := "UNUSED";
            outclock_phase_shift : natural := 0);
	port (inclock : in std_logic;
         inclocken : in std_logic := '1';
         fbin : in std_logic := '0';
         clock0 : out std_logic;
         clock1: out std_logic;