ddr_sdram.esf

用VHDL编写DDR SDRAM Controller的源代码

OPTIONS_FOR_INDIVIDUAL_NODES_ONLY
{
	BA : FAST_OUTPUT_REGISTER = ON;
	CAS_N : FAST_OUTPUT_REGISTER = ON;
	CKE : FAST_OUTPUT_REGISTER = ON;
	CS_N : FAST_OUTPUT_REGISTER = ON;
	DATAOUT : FAST_OUTPUT_REGISTER = ON;
	RAS_N : FAST_OUTPUT_REGISTER = ON;
	SA : FAST_OUTPUT_REGISTER = ON;
	WE_N : FAST_OUTPUT_REGISTER = ON;
	DATAIN : FAST_INPUT_REGISTER = ON;
	DM : FAST_INPUT_REGISTER = ON;
	DQ : FAST_INPUT_REGISTER = ON;
}
TIMING_REQUIREMENTS
{
	CLK : CLOCK_SETTINGS = CLK;
	"PLL1:pll|altclklock:altclklock_component|clock0" : CLOCK_SETTINGS = CLK100;
	CLK : CUT = OFF;
	"ddr_data_path:data_path1|DQOE" : CUT = ON;
	"ddr_data_path_3:data_path4|DQOE" : CUT = ON;
	"ddr_data_path_3:data_path4|dqs_oeb" : CUT = ON;
}