Serial UART open source core. The design is engineered for use as a stand alone chip or for use with - 免费下载

VHDL/FPGA/Verilog资源 文件大小：6 K

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Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost every machine understands it.Also, for OCRP-1, we needed a way of communication with a host computer, to make it available over the net.

源码文件列表

📂 共 9 个源码文件 点击文件名可在线查看源代码

1 📄
uart_lib.vhd
大小: 2.34 KB
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2 📄
uarttest.vhd
大小: 8.19 KB
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3 📄
clkunit.vhd
大小: 5.01 KB
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4 📄
miniuart.vhd
大小: 8.05 KB
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5 📄
rxunit.vhd
大小: 6.34 KB
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6 📄
txunit.vhd
大小: 4.66 KB
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7 📄
entries
大小: 267 B
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8 📄
repository
大小: 9 B
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9 📄
root
大小: 13 B
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