This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDR

VHDL/FPGA/Verilog 113 K 45 次下载 2014-01-19

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RAR

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113 K

资源分类

VHDL/FPGA/Verilog

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red2years

发布时间

2014-01-19 03:57

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45 次

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2 积分

This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDR - 资源详细说明

This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec

This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDR - 源码文件列表

本资源包含 25 个源码文件支持在线预览，点击文件名即可查看

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This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDR

资源详细信息

This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDR - 资源详细说明

This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDR - 源码文件列表

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