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sda.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
v1.0.0
4af25d6c4a59ec3922a21b8f6d000e27770b04cd
sgate.v
// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any o
disp.v
//
// decoder for 7 led display
//
module disp (in, out);
input [7:0] in;
output [13:0] out;
reg [13:0] out;
always @(in)
begin
case (in[7:4])
4'h0: out[13:7] = 7'b1110111;
processrxbyte.v
// File : ../RTL/serialInterfaceEngine/processRxByte.v
// Generated : 10/15/06 20:31:21
// From : ../RTL/serialInterfaceEngine/processRxByte.asf
// By : FSM2VHDL ver. 5.0
sietransmitter.v
// File : ../RTL/serialInterfaceEngine/SIETransmitter.v
// Generated : 10/15/06 20:31:22
// From : ../RTL/serialInterfaceEngine/SIETransmitter.asf
// By : FSM2VHDL ver. 5
processtxbyte.v
// File : ../RTL/serialInterfaceEngine/processTxByte.v
// Generated : 10/15/06 20:31:21
// From : ../RTL/serialInterfaceEngine/processTxByte.asf
// By : FSM2VHDL ver. 5.0
readusbwiredata.v
//////////////////////////////////////////////////////////////////////
//// ////
//// readUSBWireData.v
linecontrolupdate.v
//////////////////////////////////////////////////////////////////////
//// ////
//// lineControlUpdate.v
writeusbwiredata.v
//////////////////////////////////////////////////////////////////////
//// ////
//// writeUSBWireData.v