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(non0_2) mov sc[0] = 1 (non0_3) mov sc[1] = 1 ;; add mpr[0] = mpr[0], mpr[1] (non0_2) shl sc[0] = sc[0], iFcode add mpr[2] = mpr[2], mpr[3] (non0_3) shl sc[1] = sc[1], iFcode add mpr[4] = mpr[4],

.file "sad_altivec.c" gcc2_compiled.: .section ".rodata" .align 4 .type perms,@object .size perms,32 perms: .long 66051 .long 67438087 .long 269554195 .long 336926231 .long 134810123 .lon

/////////////////////////////////////////////////////////////////////////////// // // mem_transfer.c optimized for ia-64 by Sebastian Felis and Max Stengel, // University of Karlsruhe, Germany, 03.06.

.file "interpolate8x8_ia64.s" .pred.safe_across_calls p1-p5,p16-p63 .text .align 16 .global interpolate8x8_halfpel_h_ia64# .proc interpolate8x8_halfpel_h_ia64# interpolate8

// *********************************** // interpolate8x8_ia64.s // optimized for IA-64 // Authors : Kai K黨n // Alexander Viehl // last update : 13.7.2002 // *********************************** .

#ifdef __GNUC__ /* $Id: xvectors.S,v 1.3.6.8 2006/04/12 22:24:14 vasanth Exp $ */ /***************************************************************************** * * Copyright (c) 2004 Xilinx, Inc. Al

/*----------------------------------------------------------------------------- // $Date: 2005/11/15 23:40:58 $ // $RCSfile: boot.S,v $ //------------------------------------------------------

/*----------------------------------------------------------------------------- // $Date: 2006/04/12 18:15:26 $ // $RCSfile: cpu_init.S,v $ //--------------------------------------------------

// // Copyright (c) 2002 Xilinx, Inc. All rights reserved. // Xilinx, Inc. // // XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A // COURTESY TO YOU. BY PROVIDING THIS DESIGN, C

// // Copyright (c) 2002 Xilinx, Inc. All rights reserved. // Xilinx, Inc. // // XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A // COURTESY TO YOU. BY PROVIDING THIS DESIGN, C