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tut.vhd
-- J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\TUT.vhd
-- VHDL code created by Xilinx's StateCAD 5.03
-- Sat Oct 26 10:39:04 2002
-- This VHDL code (for use with IEEE compliant tools) was generate
tut_tb.vhd
-- J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\TUT_TB.VHD
-- VHDL testbench created by
-- Xilinx's StateBench 1.01
-- Sat Oct 26 14:41:18 2002
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBR
test_wave.tfw
// J:\PROJECTS\ISE\COREGENDEMO\DPRAM_CORE_DEMO
// Verilog Test fixture created by
// HDL Bencher 5.1i
// Wed Nov 06 18:09:22 2002
//
// Notes:
// 1) This test fixture has been automatically gen
test_wave.ant
// J:\PROJECTS\ISE\COREGENDEMO\DPRAM_CORE_DEMO
// Verilog Annotation Test Bench created by
// HDL Bencher 5.1i
// Wed Nov 06 18:09:22 2002
`timescale 1ns/1ns
module testbench;
reg [3:0] add
netlist.lst
J:\projects\ISE\CoreGenDemo\DPRAM_core_Demo\top.ngc 1036575512
J:\projects\ISE\CoreGenDemo\DPRAM_core_Demo\dpram_core.edn 1036499733
OK
alu_tst_wave.tfw
// J:\TEMP\EXAM\HDLBENCHER-ALU\ALU_VLOG
// Verilog Test fixture created by
// HDL Bencher 5.1i
// Thu Dec 19 17:46:39 2002
//
// Notes:
// 1) This test fixture has been automatically generated
alu_tst_wave.ant
// J:\TEMP\EXAM\HDLBENCHER-ALU\ALU_VLOG
// Verilog Annotation Test Bench created by
// HDL Bencher 5.1i
// Thu Dec 19 17:46:39 2002
`timescale 1ns/1ns
`define op_sub 1
`define op_and 2
`def
stmach_v.v
// J:\ISE\WATCH_SC\STMACH_V.v
// Verilog created by Xilinx's StateCAD 5.1i
// Wed Dec 04 09:42:10 2002
// This Verilog code (for use with Xilinx XST) was generated using:
// one-hot state
stmach_v.v
// J:\ISE\WATCH_SC\STMACH_V.v
// Verilog created by Xilinx's StateCAD 5.1i
// Wed Dec 04 09:42:10 2002
// This Verilog code (for use with Xilinx XST) was generated using:
// one-hot state
stmach_v.vhd
-- J:\PROJECTS\ISE\ISEEXAMPLES\WTUT_SC\STMACH_V.vhd
-- VHDL code created by Xilinx's StateCAD 5.1i
-- Tue Nov 12 09:10:01 2002
-- This VHDL code (for use with IEEE compliant tools) was genera