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jk_flip_flop.vhd
--** J K 触 发 器
--文件名：JK_flip_flop.vhd
--功 能：JK触发器
--说 明：“q”采用发光二极管来表示；
-- “set”、“reset”分别用按键S3，S4来表示；
--**注意：按键是'0'有效，默认是'1'电平； 片选信号(cs)为高电平选通；
libr
jk_flip_flop.vhd
--** J K 触 发 器
--文件名：JK_flip_flop.vhd
--功 能：JK触发器
--说 明：“q”采用发光二极管来表示；
-- “set”、“reset”分别用按键S3，S4来表示；
--**注意：按键是'0'有效，默认是'1'电平； 片选信号(cs)为高电平选通；
libr
simtut_tb.reg
| J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\SIMTUT_TB.REG
| StateBench(tm) regression file created by
| Xilinx's StateBench 1.01
| Sat Oct 26 14:36:48 2002
restart
constraint set
time_s
simtut_tb.vhd
-- J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\SIMTUT_TB.VHD
-- VHDL testbench created by
-- Xilinx's StateBench 1.01
-- Sat Oct 26 14:36:48 2002
LIBRARY ieee;
USE ieee.std_logic_1164.all;
L
tut_tb.tmp
| J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\TUT_TB.TMP
| StateBench(tm) regression file created by
| Xilinx's StateBench 1.01
| Sat Oct 26 14:47:03 2002
restart
constraint set
time_scal
tut.vhd
-- J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\TUT.vhd
-- VHDL code created by Xilinx's StateCAD 5.03
-- Sat Oct 26 10:39:04 2002
-- This VHDL code (for use with IEEE compliant tools) was generate
tut_tb.vhd
-- J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\TUT_TB.VHD
-- VHDL testbench created by
-- Xilinx's StateBench 1.01
-- Sat Oct 26 14:41:18 2002
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBR
simtut_tb.tmp
| J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\SIMTUT_TB.TMP
| StateBench(tm) regression file created by
| Xilinx's StateBench 1.01
| Sat Oct 26 14:35:37 2002
restart
constraint set
time_s
tut_tb.reg
| J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\TUT_TB.REG
| StateBench(tm) regression file created by
| Xilinx's StateBench 1.01
| Sat Oct 26 14:41:18 2002
restart
constraint set
time_scal
simtut_tb.vhd
-- J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\SIMTUT_TB.VHD
-- VHDL testbench created by
-- Xilinx's StateBench 1.01
-- Sat Oct 26 14:36:48 2002
LIBRARY ieee;
USE ieee.std_logic_1164.all;
L