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-- D:\CHENYI\SHUZIZHONG -- VHDL Annotation Test Bench created by -- HDL Bencher 6.1i -- Sun Dec 07 14:49:51 2008 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE

A, ..\SOURCE C, ..\SOURCE D, ..\DOC L, ..\LST O, ..\OBJ P, ..\PROD T, ..\TEST W, ..\WORK AIO, \SOFTWARE\BLOCKS\AI

a=1.00045e+00 b=2.75205e+00 q=5.86795e-03 s=2.30965e-02 p=1.10100e+00 umax=4.77727e-02 umin=2.04545e-03 u=1.74298e-02

a( 0)=-8.00000e-01 a( 1)=-7.00000e-01 a( 2)=5.00000e-01 a( 3)=1.07800e+01 q=1.20000e-02 s=4.89898e-02 r=7.55929e-01 v( 0)=9.98351e-01 v( 1)=9.99365e-01 v( 2)=9.99482e-01 u=1.60000e-0

a= 1.249270e+01 b= 5.619315e-10 q= 3.271371e+01 s= 1.651103e+00 umax= 5.064987e+00 umin= 1.119425e-02 u= 8.630600e-01

a= 9.415757e-01 b= 8.857726e-01 q= 1.786596e+00 s= 4.226814e-01 umax= 8.561686e-01 umin= 1.331988e-03 u= 2.506153e-01

a( 0)=5.63248e-01 a( 1)=1.38675e+00 a( 2)=-1.93134e-01 a( 3)=6.44035e-02 a( 4)=-1.68412e-02 a( 5)=3.34429e-03 dt( 0)=1.80174e-09 dt( 1)=1.68505e-04 dt( 2)=1.53940e-05

a( 0)=-1.11022e-16 a( 1)=9.95364e-01 a( 2)=1.66533e-16 a( 3)=-2.88716e-01 a( 4)=-1.66533e-16 a( 5)=7.93575e-02 MAX(p-f)=6.07072e-04

a( 0)=2.63183e+01 b( 0)=0.00000e+00 a( 1)=3.60654e+00 b( 1)=-1.26867e+01 a( 2)=6.06546e-01 b( 2)=-6.33721e+00 a( 3)=5.09912e-02 b( 3)=-4.21798e+00 a( 4)=-1.43451e-01 b( 4)=-3

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