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A 的代码
a.udo
-- ProjNav VHDL simulation template: a.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
a.vhw
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 11:28:48 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
a.fdo
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Sun Dec 07 11:28:48 中国标准时间 2008
##
vlib work
vcom -93 -explicit second.vhdl
vcom -93 -explicit a.vhw
vsim -t 1ps