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chap7_7.mdl

Model { Name "chap7_7" Version 3.00 SimParamPage "Solver" SampleTimeColors off InvariantConstants off WideVectorLines off ShowLineWidths off ShowPortDataTypes

v7_7.vhd

library ieee; use ieee.std_logic_1164.all; entity TProc is port(a : in std_logic; b : inout std_logic; o : out std_logic); end TProc; architecture A_TProc of TProc i

chap7_7.mdl

Model { Name "chap7_7" Version 3.00 SimParamPage "Solver" SampleTimeColors off InvariantConstants off WideVectorLines off ShowLineWidths off ShowPortDataTypes