AT91SAM7A1_whitepaper these are white papers for ARM
标签： whitepaper papers these white
上传时间： 2017-09-27
上传用户：PresidentHuang
pll 相關paper,可參考! 內含各模塊架構及模擬，歡迎參考!
标签： PLL
上传时间： 2015-05-10
上传用户：jeryir
for the test,to be more easier to process the paper
标签： paper reading image processing
上传时间： 2015-11-05
上传用户：wnlx0626
A型USB插座（receptacle）的封装 1 VBUS Red（红色） 2 D- White（白色） 3 D+ Green（绿色） 4 GND Black（黑色） Mini B型USB插座（receptacle） 编号 定义 颜色识别 1 VBUS Red（红色） 2 D- White（白色） 3 D+ Green（绿色） 4 ID Not connected（未连接） 5 GND Black（黑色）
上传时间： 2013-05-25
上传用户：sammi
摘要：本文主要介绍以CPLD 芯片进行十字路口的交通灯的设计，用CPLD 作为交通灯控制器的主控芯片，采用VHDL\r\n语言编写控制程序，利用CPLD的可重复编程和在动态系统重构的特性，大大地提高了数字系统设计的灵活性和通用性。\r\n关键词：CPLD；VHDL；交通灯控制器\r\n中图分类号：TP39\r\nAbstract ：This paper introduces the electronic-traffic lamp, which is based on the VHDL and is com
上传时间： 2013-08-11
上传用户：aesuser
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
标签： Efficient Verilog Digital Coding
上传时间： 2013-11-22
上传用户：han_zh
本文论述了状态机的verilog编码风格,以及不同编码风格的优缺点，Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for Synthesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.
标签： Synthesis Machine Coding Styles
上传时间： 2013-10-15
上传用户：dancnc
One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions
上传时间： 2013-10-17
上传用户：tb_6877751
This paper presents a space vector modulation(SVM)-based switching strategy for a three-level neutral point clamped (NPC) converter that is adapted as a STATCOM.
上传时间： 2013-10-20
上传用户：zyt
设计了水声信号发生系统中的功率放大电路，可将前级电路产生的方波信号转换为正弦信号，同时进行滤波、功率放大，使其满足换能器对输入信号的要求。该电路以单片机AT89C52，集成6阶巴特沃思低通滤波芯片MF6以及大功率运算放大器LM12为核心，通过标准RS232接口与PC进行通信，实现信号增益的程控调节，对干扰信号具有良好的抑制作用。经调试该电路工作稳定正常，输出波形无失真，在输出功率以及放大增益、波纹系数等方面均满足设计要求。 This paper presented a design and implementation of underwater acoustic power amplifer. This circuit converted the rectangle signal generated by frontend circuit into the sine signal， then filtered and power amplification， it meets the requirements of the transducer.Included AT89C52， 6th order Butterworth filter MF6， hipower amplififier LM12.Communication with PC through the RS232 port. The signal gain is adjustable and could be remote controlled. It has a good inhibitory effect on the interference signal. After debugged， this circuit works stable， the output waveform has no distortion， it meets the design requirement in outprt power， amplifier gain and ripple factor.
上传时间： 2013-11-20
上传用户：qwe1234
