top-down+parser技术资料下载专区，收录209份相关技术文档、开发源码、电路图纸等优质工程师资源，全部免费下载。
BSDL Description for Top-Level Entity TMS320F2812
Digital Down Converter Design based on FPGA.
Applications􀁹 On-card switching regulators􀁹 Simple high efficiency step
学习培训书籍资料 ABEL设计软件是一种高级编译型可编程逻辑设计软件， 只需要输入符合语法规定的逻辑描述，就能设计各种不同类型 的PLD器件。这种软件可以对用户的逻辑设计进行语法检查、 逻辑化简、自动生成符合标准的JEDEC文件（“．JED...
Digital Down Converter Design based on FPGA.
Up-down Asynchronous counter in Behavioral Model
The TL2575 and TL2575HV represent superior alternatives to popular three-terminal linear regulators.
The CYT3482 is a monolithic synchronous buck regulator. The device integrates 100mΩ MOSFETS that pro
ISUP protocol test suite. Useful for building ISUP parser.