%----------------------------------------------------------------------- % Example 2.7.3: DC Bridge Circuit %------------------…
timing+circuit 源代码
汇集 timing+circuit 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
--negative.vhd correct negative number circuit library ieee ; use ieee.std_logic_1164.all; use work.components.all; entity neg…
*********************************************************************** ** ** Xilinx, Inc. 2004 www.xilinx.com *…
*********************************************************************** ** ** Xilinx, Inc. 2004 www.xilinx.com *…
#ifndef _NR4_H #define _NR4_H /* nr4.h: defines for netrom layer 4 (transport) support */ #ifndef _MBUF_H #include "mbuf.h"…
/* * nr4subr.c: subroutines for net/rom transport layer. */ #include #include "global.h" #include "mbuf.h" #include "…
/********** Copyright 1990 Regents of the University of California. All rights reserved. Author: 1985 Wayne A. Christopher, U. C.…
/********** Copyright 1990 Regents of the University of California. All rights reserved. Author: 1985 Wayne A. Christopher, U. C.…
/********** Copyright 1990 Regents of the University of California. All rights reserved. Author: 1985 Thomas L. Quarles *********…
/********** Copyright 1990 Regents of the University of California. All rights reserved. Author: 1985 Thomas L. Quarles *********…