readme_vhd.txt

VHDL

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  **
  ** Xilinx, Inc. 2004          www.xilinx.com
  **
  ** XAPP194 - Serial-to-Parallel Converter
  **
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  **
  ** Filenames and Descriptions: 
  **
  **      TOP_VHD.vhd - Top level design file
  **      OUTPUT_PIPELINE.vhd -  Output multiplexor tree with pipelining. Depth determined by number of channels
  **      DELAY.vhd -  Delay elements
  **      OR4X32_REG.vhd - Mux elements
  **      RD_CNTRL.vhd -  Read control circuit
  **      S2P8X32.vhd -  Deserializer block
  **      MUX_8X1.vhd -  Steering muxes
  **      SYNC.vhd -  synchronizing circuit
  **      WR_CNTRL.vhd -  Write control circuit   
  **
  ** Date - version : 04/19/2004 - v1.0
  **
  ** Author:  Xilinx, Inc.
  **
  ** Contact: e-mail  [e-mail] phone   + 1 800 255 7778
  **
  ** Disclaimer: 
  ** LIMITED WARRANTY AND DISCLAIMER. These designs are
  ** provided to you "as is". Xilinx and its licensors make and you
  ** receive no warranties or conditions, express, implied,
  ** statutory or otherwise, and Xilinx specifically disclaims any
  ** implied warranties of merchantability, non-infringement, or
  ** fitness for a particular purpose. Xilinx does not warrant that
  ** the functions contained in these designs will meet your
  ** requirements, or that the operation of these designs will be
  ** uninterrupted or error free, or that defects in the Designs
  ** will be corrected. Furthermore, Xilinx does not warrant or
  ** make any representations regarding use or the results of the
  ** use of the designs in terms of correctness, accuracy,
  ** reliability, or otherwise.
  **
  ** LIMITATION OF LIABILITY. In no event will Xilinx or its
  ** licensors be liable for any loss of data, lost profits, cost
  ** or procurement of substitute goods or services, or for any
  ** special, incidental, consequential, or indirect damages
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  ** essential purpose of any limited remedies herein.
  **
  **  Copyright (c) 2004 Xilinx, Inc.
  **  All rights reserved
  **
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