Verilog and VHDL状态机设计，英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.
上传时间： 2013-12-19
上传用户：change0329
Our approach to understanding mobile learning begins by describing a dialectical approach to the development and presentation of a task model using the sociocognitive engineering design method. This analysis synthesises relevant theoretical approaches. We then examine two field studies which feed into the development of the task model.
标签： approach understanding dialectical describing
上传时间： 2014-11-28
上传用户：comua
Real-Time Kernel ，简易型REAL-TEME SYSTEM 源码,可用于嵌入Muti task学习
上传时间： 2014-01-14
上传用户：kbnswdifs
We have a group of N items (represented by integers from 1 to N), and we know that there is some total order defined for these items. You may assume that no two elements will be equal (for all a, b: a<b or b<a). However, it is expensive to compare two items. Your task is to make a number of comparisons, and then output the sorted order. The cost of determining if a < b is given by the bth integer of element a of costs (space delimited), which is the same as the ath integer of element b. Naturally, you will be judged on the total cost of the comparisons you make before outputting the sorted order. If your order is incorrect, you will receive a 0. Otherwise, your score will be opt/cost, where opt is the best cost anyone has achieved and cost is the total cost of the comparisons you make (so your score for a test case will be between 0 and 1). Your score for the problem will simply be the sum of your scores for the individual test cases.
标签： represented integers group items
上传时间： 2016-01-16
上传用户：jeffery
As all of you know, MATLAB is a powerful engineering language. Because of some limitation, some tasks take very long time to proceed. Also MATLAB is an interpreter not a compiler. For this reason, executing a MATLAB program (m file) is time consuming. For solving this problem, Mathworks provides us C Math Library or in common language, MATLAB API. A developer can employ these APIs to solve engineering problems very fast and easy. This article is about how can use these APIs.
标签： some engineering limitation language
上传时间： 2013-12-06
上传用户：huql11633
定时中断程序，源码的注释十分详细，具体功能如下： 1.Frame 实现能有效降低VxWorks 内存管理内部/外部碎片的机制。 2. Frame 实现为系统提供软定时器功能的机制，定时器timeout 信息以message 或其他快捷有效方式通知定时器申请者（task）。 3. 参考实验一要求，系统中每个task 拥有自己的Message Queue，以此方式作为系统的消息驱动基础。 4. 系统中各task 应使用同一类型框架，即统一的task 框架。 5. 系统内实体（task/ISR）间传递的消息应有统一格式（消息头+消息体），可分短消息和长消息，但消息头须至少包含消息ID。系统内所有消息均有其唯一ID 标识。
上传时间： 2016-04-02
上传用户：BOBOniu
The IA-32 Software Developer’s Manual, Volume 3: System Programming Guide (Order Number 245472), is part of a three-volume set that describes the architecture and programming environment of all IA-32 Intel® Architecture processors. The IA-32 Software Developer’s Manual, Volume 3, describes the operating-system support environment of an IA-32 processor, including memory management, protection, task management, interrupt and exception handling, and system management mode. It also provides IA-32 processor compatibility information. This volume is aimed at operating- system and BIOS designers and programmers.
标签： Programming Developer Software 245472
上传时间： 2013-12-23
上传用户：小码农lz
在了解实时嵌入式操作系统内存管理机制的特点以及实时处理对内存管理需求的基础上，练习并掌握有效处理内存碎片的内存管理机制，同时理解防止内存泄漏问题的良好设计方法。使用预先规划的思想，构建自己的私有内存管理机制，在系统内存池中申请内存，并将其纳入私有内存管理机制中，形成静态预分配内存池； 静态预分配内存池支持一种以上固定长度内存池，如16 字节内存池和256 字节内存池。固定长度内存池的单块长度应考虑体系结构开销，并尽量减少内部碎片；固定长度内存池数量应可配置； 静态预分配内存池与系统内存池的统一管理机制。向用户分配内存时应保证长度最佳匹配原则。当申请内存的长度超过静态预分配长度或资源不足时，自动向系统内存池申请； 管理机制包括： a) 初 始化函数； b) 内 存申请/释放函数。并特别要保证释放安全； c) 告 警机制； d) 管 理监视机制。 5. 利用可能的互斥机制或代码可重入设计，保证以上管理机制的操作安全性； 6. 创建多task 环境测试及演示以上内容
上传时间： 2016-04-12
上传用户：lizhen9880
JRemoteControl is a simple Java™ driven bluetooth remote control.It allows you to initiate virtually any task on your PC from a J2ME enabled device.
标签： JRemoteControl bluetooth initiate control
上传时间： 2016-04-21
上传用户：1583060504
北京大学ACM比赛题目 In 1742, Christian Goldbach, a German amateur mathematician, sent a letter to Leonhard Euler in which he made the following conjecture: Every even number greater than 4 can be written as the sum of two odd prime numbers. For example: 8 = 3 + 5. Both 3 and 5 are odd prime numbers. 20 = 3 + 17 = 7 + 13. 42 = 5 + 37 = 11 + 31 = 13 + 29 = 19 + 23. Today it is still unproven whether the conjecture is right. (Oh wait, I have the proof of course, but it is too long to write it on the margin of this page.) Anyway, your task is now to verify Goldbach s conjecture for all even numbers less than a million.
标签： mathematician Christian Goldbach Leonhard
上传时间： 2016-04-21
上传用户：wangchong
