The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, submicron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basics of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.
标签： application real-time Synopsys emphasis
上传时间： 2017-07-05
上传用户：waitingfy
本系统分电压测量和信号产生输出两大部分，电压测量部分以模拟电路为主，配合放大模块、A/D转化模块、显示模块；通过凌阳单片机进行数据处理，在误差允许范围内显示测量电压值。信号产生以直接数字式频率合成器(Direct Digital Frequency synthesis,简称DDS或DDFS)为核心，经过AT89S52对DDS芯片内部进行控制，使之输出标准正弦波形，利用编程实现频率预置、步进，达到电压输出频率的可调节步进。通过调试与测量完成了题目的基本部分和全部发挥部分的要求并有自己的创新
上传时间： 2017-08-08
上传用户：comua
频率合成技术在现代电子技术中具有重要的地位。在通信、雷达和导航等设备中，它可以作为干扰信号发生器；在测试设备中，可作为标准信号源，因此频率合成器被人们称为许多电子系统的“心脏”。直接数字频率合成（DDS——Digital Direct Frequency synthesis）技术是一种全新的频率合成方法，是频率合成技术的一次革命。本文主要分析了DDS的基本原理及其输出频谱特点，并采用VHDL语言在FPGA上实现。对于DDS的输出频谱，一个较大的缺点是：输出杂散较大。针对这一缺点本文使用了两个方法加以解决。首先是压缩ROM查找表，
上传时间： 2017-09-28
上传用户：大三三
《分析性写作》，介绍言简意赅： The popular, brief rhetoric that treats writing as thinking, WRITING ANALYTICALLY, Sixth Edition, offers a series of prompts that lead you through the process of analysis and synthesis and help you to generate original and well-developed ideas. The book's overall point is that learning to write well means learning to use writing as a way of thinking well. To that end, the strategies of this book describe thinking skills that employ writing. As you will see, this book treats writing as a tool of thought--a means of undertaking sustained acts of inquiry and reflection.
上传时间： 2015-08-22
上传用户：东大寺的
Lithium–sulfur batteries are a promising energy-storage technology due to their relatively low cost and high theoretical energy density. However, one of their major technical problems is the shuttling of soluble polysulfides between electrodes, resulting in rapid capacity fading. Here, we present a metal–organic framework (MOF)-based battery separator to mitigate the shuttling problem. We show that the MOF-based separator acts as an ionic sieve in lithium–sulfur batteries, which selectively sieves Li+ ions while e ciently suppressing undesired polysulfides migrating to the anode side. When a sulfur-containing mesoporous carbon material (approximately 70 wt% sulfur content) is used as a cathode composite without elaborate synthesis or surface modification, a lithium–sulfur battery with a MOF-based separator exhibits a low capacity decay rate (0.019% per cycle over 1,500 cycles). Moreover, there is almost no capacity fading after the initial 100 cycles. Our approach demonstrates the potential for MOF-based materials as separators for energy-storage applications.
上传时间： 2017-11-23
上传用户：653357637
Synopsys' widely-used design constraints format, known as SDC, describes the "design intent" and surrounding constraints for synthesis, clocking, timing, power, test and environmental and operating conditions. SDC has been in use and evolving for more than 20 years, making it the most popular and proven format for describing design constraints. Essentially all synthesized designs use SDC and numerous EDA companies have translators that can read and process SDC.
上传时间： 2018-07-13
上传用户：yalsim
特别好的教程特别好的教程 Research progress in synthesis and modification of polylactic acid Research progress in synthesis and modification of polylactic acid
标签： 教程
上传时间： 2021-09-17
上传用户：陈浩
The Verilog Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.
上传时间： 2021-11-09
上传用户：
电子书-RTL Design Style Guide for Verilog HDL540页A FF having a fixed input value is generated from the description in the upper portion of Example 2-21. In this case, ’0’ is output when the reset signal is asynchronously input, and ’1’ is output when the START signal rises. Therefore, the FF data input is fixed at the power supply, since the typical value ’1’ is output following the rise of the START signal. When FF input values are fixed, the fixed inputs become untestable and the fault detection rate drops. When implementing a scan design and converting to a scan FF, the scan may not be executed properl not be executed properly, so such descriptions , so such descriptions are not are not recommended. recommended.[1] As in the lower part of Example 2-21, be sure to construct a synchronous type of circuit and ensure that the clock signal is input to the clock pin of the FF. Other than the sample shown in Example 2-21, there are situations where for certain control signals, those that had been switched due to the conditions of an external input will no longer need to be switched, leaving only a FF. If logic exists in a lower level and a fixed value is input from an upper level, the input value of the FF may also end up being fixed as the result of optimization with logic synthesis tools. In a situation like this, while perhaps difficult to completely eliminate, the problem should be avoided as much as possible.
标签： RTL verilog hdl
上传时间： 2022-03-21
上传用户：canderile
本文主要介绍如何在Wado设计套件中进行时序约束，原文出自 xilinx中文社区。1 Timing Constraints in Vivado-UCF to xdcVivado软件相比于sE的一大转变就是约束文件，5E软件支持的是UcF（User Constraints file，而 Vivado软件转换到了XDc（Xilinx Design Constraints）。XDC主要基于SDc（Synopsys Design Constraints）标准，另外集成了Xinx的一些约束标准可以说这一转变是xinx向业界标准的靠拢。Altera从 TimeQuest开始就一直使用SDc标准，这一改变，相信对于很多工程师来说是好事，两个平台之间的转换会更加容易些。首先看一下业界标准SDc的原文介绍：Synopsys widely-used design constraints format, known as sDc, describes the design intent"and surrounding constraints for synthesis, clocking, timing, power, test and environmental and operating conditions. sDc has been in use and evolving for more than 20 years, making it the most popular and proven format for describing design constraints. Essentially all synthesized designs use SDc and numerous EDa companies have translators that can read and process sDc
标签： vivado
上传时间： 2022-03-26
上传用户：
