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  • LPC1850 Cortex-M3内核微控制器数据手册

    The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.

    标签: Cortex-M 1850 LPC 内核微控制器

    上传时间: 2014-12-31

    上传用户:zhuoying119

  • LPC4300系列ARM双核微控制器产品数据手册

    The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals

    标签: 4300 LPC ARM 双核微控制器

    上传时间: 2013-10-28

    上传用户:15501536189

  • PCB阻抗匹配计算工具(附教程)

    附件是一款PCB阻抗匹配计算工具,点击CITS25.exe直接打开使用,无需安装。附件还带有PCB连板的一些计算方法,连板的排法和PCB联板的设计验验。 PCB设计的經驗建議:       1.一般連板長寬比率為1:1~2.5:1,同時注意For FuJi Machine:a.最大進板尺寸為:450*350mm,       2.針對有金手指的部分,板邊處需作掏空處理,建議不作為連板的部位.     3.連板方向以同一方向為優先,考量對稱防呆,特殊情況另作處理.     4.連板掏空長度超過板長度的1/2時,需加補強邊.       5.陰陽板的設計需作特殊考量.       6.工藝邊需根據實際需要作設計調整,軌道邊一般不少於6mm,實際中需考量板邊零件的排布,軌道設備正常卡壓距離為不少於3mm,及符合實際要求下的連板經濟性.       7.FIDUCIAL MARK或稱光學定位點,一般設計在對角處,為2個或4個,同時MARK點面需平整,無氧化,脫落現象;定位孔設計在板邊,為對稱設計,一般為4個,直徑為3mm,公差為±0.01inch.       8.V-cut深度需根據連板大小及基板板厚考量,角度建議為不少於45°.       9.連板設計的同時,需基於基板的分板方式考量<人工(治具)還是使用分板設備>.  10.使用針孔(郵票孔)聯接:需請考慮斷裂后的毛刺,及是否影響COB工序的Bonding机上的夾具穩定工作,還應考慮是否有無影響插件過軌道,及是否影響裝配組裝. 

    标签: PCB 阻抗匹配 计算工具 教程

    上传时间: 2014-12-31

    上传用户:sunshine1402

  • 单片机12864液晶时钟显示程序

    12864液晶时钟显示程序 LCD 地址变量 ;**************变量的定义***************** RS             BIT      P2.0            ;LCD数据/命令选择端(H/L) RW             BIT      P2.1          ;LCD读/写选择端(H/L) EP             BIT      P2.2            ;LCD使能控制 PSB        EQU P2.3 RST        EQU P2.5 PRE            BIT      P1.4            ;调整键(K1) ADJ            BIT      P1.5            ;调整键(K2) COMDAT         EQU P0 LED        EQU P0.3 YEAR           DATA      18H            ;年,月,日变量 MONTH          DATA      19H DATE           DATA      1AH WEEK           DATA      1BH HOUR           DATA      1CH            ;时,分,秒,百分之一秒变量 MIN            DATA      1DH SEC            DATA      1EH SEC100         DATA      1FH STATE          DATA      23H LEAP           BIT      STATE.1            ;是否闰年标志1--闰年,0--平年 KEY_S          DATA      24H            ;当前扫描键值 KEY_V          DATA      25H            ;上次扫描键值 DIS_BUF_U0      DATA      26H            ;LCD第一排显示缓冲区 DIS_BUF_U1      DATA      27H DIS_BUF_U2      DATA      28H DIS_BUF_U3      DATA      29H DIS_BUF_U4      DATA      2AH DIS_BUF_U5      DATA      2BH DIS_BUF_U6      DATA      2CH DIS_BUF_U7      DATA      2DH DIS_BUF_U8      DATA      2EH DIS_BUF_U9      DATA      2FH DIS_BUF_U10     DATA      30H DIS_BUF_U11     DATA      31H DIS_BUF_U12     DATA      32H DIS_BUF_U13     DATA      33H DIS_BUF_U14     DATA      34H DIS_BUF_U15     DATA      35H DIS_BUF_L0      DATA      36H            ;LCD第三排显示缓冲区 DIS_BUF_L1      DATA      37H DIS_BUF_L2      DATA      38H DIS_BUF_L3      DATA      39H DIS_BUF_L4      DATA      3AH DIS_BUF_L5      DATA      3BH DIS_BUF_L6      DATA      3CH DIS_BUF_L7      DATA      3DH DIS_BUF_L8      DATA      3EH DIS_BUF_L9      DATA      3FH DIS_BUF_L10     DATA      40H DIS_BUF_L11     DATA      41H DIS_BUF_L12     DATA      42H DIS_BUF_L13     DATA      43H DIS_BUF_L14     DATA      44H DIS_BUF_L15     DATA      45H FLAG            DATA      46H ;1-年,2-月,3-日,4-时,5-分,6-秒,7-退出调整。 DIS_H           DATA      47H DIS_M           DATA      48H DIS_S           DATA      49H

    标签: 12864 单片机 液晶时钟 显示程序

    上传时间: 2013-11-09

    上传用户:xingisme

  • Foundation入门—仿真

    Explain how to open the Waveform Viewer for Verification ? State how to insert nodes into the Waveform Viewer ? Tell how to assign Stimulus with the Stimulator Selector

    标签: Foundation 仿真

    上传时间: 2013-11-05

    上传用户:gps6888

  • PCB阻抗匹配计算工具(附教程)

    附件是一款PCB阻抗匹配计算工具,点击CITS25.exe直接打开使用,无需安装。附件还带有PCB连板的一些计算方法,连板的排法和PCB联板的设计验验。 PCB设计的經驗建議:       1.一般連板長寬比率為1:1~2.5:1,同時注意For FuJi Machine:a.最大進板尺寸為:450*350mm,       2.針對有金手指的部分,板邊處需作掏空處理,建議不作為連板的部位.     3.連板方向以同一方向為優先,考量對稱防呆,特殊情況另作處理.     4.連板掏空長度超過板長度的1/2時,需加補強邊.       5.陰陽板的設計需作特殊考量.       6.工藝邊需根據實際需要作設計調整,軌道邊一般不少於6mm,實際中需考量板邊零件的排布,軌道設備正常卡壓距離為不少於3mm,及符合實際要求下的連板經濟性.       7.FIDUCIAL MARK或稱光學定位點,一般設計在對角處,為2個或4個,同時MARK點面需平整,無氧化,脫落現象;定位孔設計在板邊,為對稱設計,一般為4個,直徑為3mm,公差為±0.01inch.       8.V-cut深度需根據連板大小及基板板厚考量,角度建議為不少於45°.       9.連板設計的同時,需基於基板的分板方式考量<人工(治具)還是使用分板設備>.  10.使用針孔(郵票孔)聯接:需請考慮斷裂后的毛刺,及是否影響COB工序的Bonding机上的夾具穩定工作,還應考慮是否有無影響插件過軌道,及是否影響裝配組裝. 

    标签: PCB 阻抗匹配 计算工具 教程

    上传时间: 2013-10-15

    上传用户:3294322651

  • 采用TÜV认证的FPGA开发功能安全系统

    This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 图Figure 1. Local Safety System

    标签: FPGA 安全系统

    上传时间: 2013-11-14

    上传用户:zoudejile

  • XAPP143-利用Verilog来创建CPLD设计

    This Application Note covers the basics of how to use Verilog as applied to ComplexProgrammable Logic Devices. Various combinational logic circuit examples, such asmultiplexers, decoders, encoders, comparators and adders are provided. Synchronous logiccircuit examples, such as counters and state machines are also provided.

    标签: Verilog XAPP CPLD 143

    上传时间: 2013-11-11

    上传用户:y13567890

  • 基于FPGA+DSP模式的智能相机设计

    针对嵌入式机器视觉系统向独立化、智能化发展的要求,介绍了一种嵌入式视觉系统--智能相机。基于对智能相机体系结构、组成模块和图像采集、传输和处理技术的分析,对国内外的几款智能相机进行比较。综合技术发展现状,提出基于FPGA+DSP模式的硬件平台,并提出智能相机的发展方向。分析结果表明,该系统设计可以实现脱离PC运行,完成图像获取与分析,并作出相应输出。 Abstract:  This paper introduced an embedded vision system-intelligent camera ,which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture, component modules and image acquisition, transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad, the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design, the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.

    标签: FPGA DSP 模式 智能相机

    上传时间: 2013-11-14

    上传用户:无聊来刷下

  • 开关电源EMI设计(英文版)

    Integrated EMI/Thermal Design forSwitching Power SuppliesWei ZhangThesis submitted to the Faculty of theVirginia Polytechnic Institute and State Universityin partial fulfillment of the requirements for the degree of Integrated EMI/Thermal Design forSwitching Power SuppliesWei Zhang(ABSTRACT)This work presents the modeling and analysis of EMI and thermal performancefor switch power supply by using the CAD tools. The methodology and design guidelinesare developed.By using a boost PFC circuit as an example, an equivalent circuit model is builtfor EMI noise prediction and analysis. The parasitic elements of circuit layout andcomponents are extracted analytically or by using CAD tools. Based on the model, circuitlayout and magnetic component design are modified to minimize circuit EMI. EMI filtercan be designed at an early stage without prototype implementation.In the second part, thermal analyses are conducted for the circuit by using thesoftware Flotherm, which includes the mechanism of conduction, convection andradiation. Thermal models are built for the components. Thermal performance of thecircuit and the temperature profile of components are predicted. Improved thermalmanagement and winding arrangement are investigated to reduce temperature.In the third part, several circuit layouts and inductor design examples are checkedfrom both the EMI and thermal point of view. Insightful information is obtained.

    标签: EMI 开关电源 英文

    上传时间: 2013-11-16

    上传用户:萍水相逢