This a CY7C68013 (USB2.0 Chip) Configuration example for Slave FIFO Mode with Sync Signal.
This a CY7C68013 (USB2.0 Chip) Configuration example for Slave FIFO Mode with Sync Signal.
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This a CY7C68013 (USB2.0 Chip) Configuration example for Slave FIFO Mode with Sync Signal.
This an USB2.0 chip CY7C68013 Configuraion Example for Slave FIFO mode with "async" mode.
此资源是Ethercat 从站协议生成工具,可方便的生成从站协议代码,配合LAN9252的相关工具和资料,能方便的地实现Ethercat从机。
MSP-FET430P140 Demo - USART1, SPI Full-Duplex 3-Wire Master P1.x Exchange
BLUETOOTH UART/USB 通信(SPP,Cable Replacement)Master端源代码.
Master the essentials of concurrent programming,including testing and debugging This textbook examines languages and ...
用户接口Wishbone bus 接口, 驱动LPC master去主动访问 slave 寄存器表(地址可更改) 读取到寄存器封装到用户层 可按要求更改设计