源码文件
devider.vhdsim_par -- generated only for ProjNav status tracking Simulation Model Target: Generic_VHDL
simulation+tracking 源代码
汇集 simulation+tracking 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
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源码文件
KeypadScan.versim_par -- generated only for ProjNav status tracking Simulation Model Target: Generic_Verilog
源码文件
can_top.vhdsim_xlate -- generated only for ProjNav status tracking Simulation Model Target: Generic_VHDL
源码文件
pn.vhdsim_par -- generated only for ProjNav status tracking Simulation Model Target: ModelSim SE (VHDL)
源码文件
cancommunication.vhdsim_par -- generated only for ProjNav status tracking Simulation Model Target: ModelSim SE (VHDL)
源码文件
szz.vhdsim_map -- generated only for ProjNav status tracking Simulation Model Target: Generic_VHDL
源码文件
bit_add.vhdsim_map -- generated only for ProjNav status tracking Simulation Model Target: Generic_VHDL
源码文件
can_top.vhdsim_xlate -- generated only for ProjNav status tracking Simulation Model Target: Generic_VHDL
源码文件
digital_clk.vhdsim_par -- generated only for ProjNav status tracking Simulation Model Target: ModelSim SE (VHDL)
源码文件
crc.vhdsim_par -- generated only for ProjNav status tracking Simulation Model Target: ModelSim SE (VHDL)