Asynchrounous pages with Ajax to refresh the page without postback
标签： Asynchrounous postback refresh without
上传时间： 2017-09-10
上传用户：龙飞艇
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT). The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset. If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on. In this example the system is clocked by the HSE(8MHz).
上传时间： 2013-11-10
上传用户：gundamwzc
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-23
上传用户：shen_dafa
一个利用三层开发的简单聊天室，发言可以自定义颜色和表情，消息保持用的是Sql数据库，采用 <meta http-equiv="refresh" content="5" />自动刷新。 DB_51aspx下为Sql数据库文件，附加即可 /login.aspx为登陆页，默认登陆帐号/密码：51aspx/51aspx
标签：
上传时间： 2013-12-25
上传用户：gengxiaochao
第四章 MATLAB 图形对象操作 4.1 图形对象的属性 4.2 图形对象句柄的获取 4.2.1 对象创建时获取 4.2.2 层次关系来获取 4.2.3 当前对象的获取 4.2.4 根据对象属性值的获取 4.3 图形对象句柄的删除与判断 4.3.1 句柄的删除 4.3.2 句柄的判断 4.4 图形对象属性值的获取与设置 4.4.1 图形对象属性值的设置 4.4.2 图形对象属性值的获取 4.4.3 用户缺省值的操作 4.5 图形对象的其它操作 4.5.1 figflag 函数 4.5.2 findfigs 函数 4.5.3 copyobj 函数 4.5.4 capture 函数 4.5.5 refresh 函数 4.5.6 saveas 函数 4.5.7 hgload 函数和 hgsave 函数 4.5.8 newplot 函数
上传时间： 2014-01-01
上传用户：cccole0605
远程控制 以前在给别人介绍Windows CE的开发时，为了演示设备上程序的运行情况，就用Remote Zoomin来截屏，设备端一刷新，Remote Zoomin就得去手动refresh一下，在CE和PC两边忙得不亦乐乎。当时就想，要是有自动刷新的功能不就省去了这么多麻烦吗。如果能在PC端直接控制CE设备，岂不更好？
上传时间： 2016-12-17
上传用户：Pzj
This is a simple image sender to a FTP site. it can be usefull if you want to send a Web-CAM frame to a FTP site, and you can refresh this image in some intervals. give a try.
标签： Web-CAM usefull simple sender
上传时间： 2013-12-24
上传用户：zhangzhenyu
form = new_form(fields) scale_form(form, &rows, &cols) win = newwin(rows+3, cols+4, 3, 20) subwin = derwin(win, rows, cols, 1, 2) set_form_sub(form, subwin) box(win, 0, 0) keypad(win, TRUE) post_form(form) refresh() wrefresh(win) wrefresh(subwin) //设置覆盖模式 form_driver(form, REQ_OVL_MODE)
标签： form cols rows scale_form
上传时间： 2017-06-11
上传用户：wff
//初始化 if(initscr() == NULL) { perror("initcurs") exit(EXIT_FAILURE) } //设置模式 cbreak() noecho() keypad(stdscr, TRUE) //建立窗口 win = newwin(h, w, 3, 20) box(win, 0, 0) keypad(win, TRUE) wmove(win, cury, curx) mvaddstr(16, 1, "Press arrow keys to move the cursor within the window.\n") mvaddstr(17, 1, "Press q to quit.\n") refresh() wrefresh(win)
标签： EXIT_FAILURE initcurs initscr perror
上传时间： 2013-12-19
上传用户：FreeSky
