This computes an in-place complex-to-complex FFT x and y are the real and imaginary arrays of 2^m points. dir = 1 gives forward transform dir = -1 gives reverse transform
标签： complex-to-complex and imaginary computes
上传时间： 2013-12-18
上传用户：huql11633
A Matlab toolbox for exact linear time-invariant system identification is presented. The emphasis is on the variety of possible ways to implement the mappings from data to parameters of the data generating system. The considered system representations are input/state/output, difference equation, and left matrix fraction. KEYWORDS: subspace identification, deterministic subspace identification, balanced model reduction, approximate system identification, MPUM.
标签： identification time-invariant presented emphasis
上传时间： 2013-12-28
上传用户：wfl_yy
Add myaa.m to your path and enjoy anti-aliased professionally looking graphics in Matlab at any time. Myaa works with any kind of graphic (3-D, plots, scatterplots, ...) and even adds anti-aliasing to text, ui controls and grids. Myaa is ideal for complex, cluttered and saturated plots.
标签： professionally anti-aliased graphics looking
上传时间： 2016-09-22
上传用户：宋桃子
Linux下头文件time.h的实现源码
上传时间： 2016-09-29
上传用户：lhc9102
Time domain FIR filter!
上传时间： 2016-10-01
上传用户：hakim
arm time 调试程序。含中断。初学者有大用。交流。
上传时间： 2016-10-02
上传用户：aysyzxzm
uc/os在lpc2100系列的KEIL模板 uc/os在lpc2100系列的real view模板 uc/os在lpc210X系列的real view模板
上传时间： 2016-10-06
上传用户：330402686
FM1702的例子程序 Chip type : ATmega16L Program type : Application Clock frequency : 7.372800 MHz Memory model : Small External SRAM size : 0 Data Stack size : 256
标签： type Application frequency 7.372800
上传时间： 2016-10-08
上传用户：chfanjiang
A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
标签： simulation Verilog writing clock
上传时间： 2016-10-12
上传用户：王者A
Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考.
标签： Clock_Dithering_Verilog u_dither Verilog Clock
上传时间： 2013-12-09
上传用户：
