Design Compiler Register Re-mapping
标签： Re-mapping Compiler Register Design
上传时间： 2019-04-03
上传用户：zsx097
复位开关： 两脚的。主板上对应位置的插针附近的英文缩写一般为RESET、RST、RS或RE等。不分正负，插反了也一样有效。 电源灯： 连线也是两脚插头，其中一根连线一般用绿色表示，另一根连线为
上传时间： 2013-04-24
上传用户：ve3344
MPC755 and MPC745 PowerPC microprocessors are high-performance, low-power, 32-bit implementations of
上传时间： 2013-05-26
上传用户：330402686
Abstract: This application note describes how sampling clock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling clock and describes a method for generating a properbroadband jittered clock. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sampleclock implementations.
上传时间： 2013-10-25
上传用户：banyou
在无线通信系统全面进入3G并开始迈向 4G的过程中，使用数字预失真技术（Digital Pre-distortion，以下简称DPD）对发射机的功放进行线性化是一门关键技术。功率放大器是通信系统中影响系统性能和覆盖范围的关键部件，非线性是功放的固有特性。非线性会引起频谱增长(spectral re-growth)，从而造成邻道干扰，使带外杂散达不到协议标准规定的要求。非线性也会造成带内失真，带来系统误码率增大的问题。
上传时间： 2013-10-19
上传用户：yy_cn
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2013-10-15
上传用户：busterman
Alkaline batteries are convenient because they’re easy tofi nd and relatively inexpensive, making them the powersource of choice for portable instruments and devicesused for outdoor recreation. Their long shelf life alsomakes them an excellent choice for emergency equipmentthat may see infrequent use but must be ready to go on amoment’s notice. It is important that the DC/DC convertersin portable devices operate over the widest possiblebattery voltage range to extend battery run time, and thussave the user from frequent battery replacement.
上传时间： 2014-12-24
上传用户：569342831
本设计是以STC89C52RC芯片为核心，利用Keil UV4编写软件和STC_ISP烧写软件，设计出一个八音盒。八音盒主要由五大模块构成，包括单片机最小系统、4*4矩阵键盘、蜂鸣器发生电路和4位数码管显示电路。有8个按键对应8首曲目播放按钮，另外8个按键对应do、re、mi、fa、so、la、si、do’八中音调。本设计主要使用单片机的内部定时器0和中断产生不同频率的方波和延时驱动蜂鸣器，并采取行列反转扫描法识别键盘键值。由于使用的是实验箱已经固化的电路，本设计主要从软件设计上加以优化，以使蜂鸣器产生的音乐更纯净。最终实现的基础功能是任意播放8首单片机内已存曲目，发挥部分是另外实现8个可演奏的琴键，使八音盒具有放音和简单演奏的两重功能，并辅以数码管显示当前播放曲目号，经过优化和调试，音色较好，琴键发音比较纯正，初步达到设计要求。
上传时间： 2013-11-18
上传用户：450976175
PIC 单片机的组成习题解答 解答部分1. PIC 单片机指令的执行过程遵循着一种全新哈佛总线体系结构的原则，充分利用了计算机系统在程序存储器和数据存储器之间地址空间的相互独立性，取指过程和执行指令过程可以流水线操作同时进行。因此，当PIC 时钟频率为4MHZ时，执行一条非转移类指令需要4 个系统时钟周期，即1us,但其指令执行的真实时间应为2us(在执行n—1 条指令时取第n 条指令，然后执行第n 条指令)。所以选项B 正确2. 端口RE 共有3 个引脚RE0~RE2，它们除了用做普通I/O 引脚和第5~7 路模拟信号输入引脚外，还依次分别承担并行口读出/写入/片选控制端引脚。A． 对。读出/写入（REO~RE1）。B．错。同步串行的相关引脚与端口C 有关。C．错。通用异步/同步串行的相关引脚与端口C有关。D． 错。CCP模块的相关引脚也是与端口C有关。所以选项A正确。3. 上电延时电路能提供一个固定的72ms 上电延时，从而使VDD有足够的时间上繁荣昌盛到单片机合适的工作电压。所以选项B 正确。
上传时间： 2013-11-09
上传用户：glxcl
Virtex-5, Spartan-DSP FPGAs Application Note This application note demonstrates how efficient implementations of Digital Up Converters(DUC) and Digital Down Converters (DDC) can be done by leveraging the Xilinx DSP IPportfolio for increased productivity and reduced time to development. Step-by-step instruction is given on how to perform system-level trade off analysis and develop the most efficient FPGA implementation, thus allowing engineers a flexible, low-cost and low-power alternative to ASSP technologies.
标签： Spartan-DSP Virtex FPGAs Ap
上传时间： 2013-10-23
上传用户：raron1989
