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其他 This code converts a Galois Field array created usin GF(2^m) for a given primitive polynomial into a
This code converts a Galois Field array created usin GF(2^m) for a given primitive polynomial into a decimal array that can be used within typical .m file coding.
Java书籍 Use a one-dimensional array of primitive type boolean to represent the seating chart of the plane.
Use a one-dimensional array of primitive type boolean to represent the seating chart of the
plane. Initialize all the elements of the array to false to indicate that all the seats are
empty. As each seat is assigned, set the corresponding elements of the array to true to
indicate that the seat is no ...
教程资料 Verilog_HDL的基本语法详解（夏宇闻版）
        Verilog_HDL的基本语法详解（夏宇闻版）:Verilog HDL是一种用于数字逻辑电路设计的语言。用Verilog HDL描述的电路设计就是该电路的Verilog HDL模型。Verilog HDL既是一种行为描述的语言也是一种结构描述的语言。这也就是说，既可以用电路的功能描述也可以用元器件和它们之 ...
教程资料 XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器
 
Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum ...
教程资料 DS306-PPC405 Virtex-4 Wrapper
The PPC405 Virtex-4 is a wrapper around the Virtex-4PowerPC™ 405 Processor Block primitive. For detailsregarding the PowerPC 405, see the PowerPC 405 ProcessorBlock Reference Guide.
可编程逻辑 Verilog_HDL的基本语法详解（夏宇闻版）
        Verilog_HDL的基本语法详解（夏宇闻版）:Verilog HDL是一种用于数字逻辑电路设计的语言。用Verilog HDL描述的电路设计就是该电路的Verilog HDL模型。Verilog HDL既是一种行为描述的语言也是一种结构描述的语言。这也就是说，既可以用电路的功能描述也可以用元器件和它们之 ...
可编程逻辑 DS306-PPC405 Virtex-4 Wrapper
The PPC405 Virtex-4 is a wrapper around the Virtex-4PowerPC™ 405 Processor Block primitive. For detailsregarding the PowerPC 405, see the PowerPC 405 ProcessorBlock Reference Guide.
可编程逻辑 XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器
 
Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum ...
VHDL/FPGA/Verilog Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols.
Hard-decision decoding scheme
Codeword length (n) : 31 symbols.
Message length (k) : 19 symbols.
Error correction capability (t) : 6 symbols
One symbol represents 5 bit.
Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^ ...
Linux/Unix编程 The main purpose of this project is to add a new scheduling algorithm to GeekOS and to implement a s
The main purpose of this project is to add a new scheduling algorithm to GeekOS and to implement a simple synchronization primitive (semaphore). As you might have already noticed, GeekOS uses a simple priority based preemptive Round Robin algorithm. In this project, you will change this to a multile ...