针对传统集成电路（ASIC）功能固定、升级困难等缺点，利用FPGA实现了扩频通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核实现NCO模块，在下变频模块调用了硬核乘法器并引入CIC滤波器进行低通滤波，给出了DQPSK解调的原理和实现方法，推导出一种简便的引入?仔/4固定相移的实现方法。采用模块化的设计方法使用VHDL语言编写出源程序，在Virtex-II Pro 开发板上成功实现了整个系统。测试结果表明该系统正确实现了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
上传时间： 2013-11-19
上传用户：neu_liyan
为了在CDMA系统中更好地应用QDPSK数字调制方式，在分析四相相对移相（QDPSK)信号调制解调原理的基础上，设计了一种QDPSK调制解调电路，它包括串并转换、差分编码、四相载波产生和选相、相干解调、差分译码和并串转换电路。在MAX+PLUSⅡ软件平台上，进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中，测试结果表明，调制电路能正确选相，解调电路输出数据与QDPSK调制输入数据完全一致，达到了预期的设计要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
上传时间： 2013-10-28
上传用户：jyycc
UART 4 UART参考设计，Xilinx提供VHDL代码 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
上传时间： 2013-11-02
上传用户：18862121743
Frequently, voltage reference stability and noise defi nemeasurement limits in instrumentation systems. In particular,reference noise often sets stable resolution limits.Reference voltages have decreased with the continuingdrop in system power supply voltages, making referencenoise increasingly important. The compressed signalprocessing range mandates a commensurate reductionin reference noise to maintain resolution. Noise ultimatelytranslates into quantization uncertainty in A to D converters,introducing jitter in applications such as scales, inertialnavigation systems, infrared thermography, DVMs andmedical imaging apparatus. A new low voltage reference,the LTC6655, has only 0.3ppm (775nV) noise at 2.5VOUT.Figure 1 lists salient specifi cations in tabular form. Accuracyand temperature coeffi cient are characteristic ofhigh grade, low voltage references. 0.1Hz to 10Hz noise,particularly noteworthy, is unequalled by any low voltageelectronic reference.
上传时间： 2013-10-30
上传用户：wxhwjf
在Multisim 10软件环境下，设计一种由运算放大器构成的精确可控矩形波信号发生器，结合系统电路原理图重点阐述了各参数指标的实现与测试方法。通过改变RC电路的电容充、放电路径和时间常数实现了占空比和频率的调节，通过多路开关投入不同数值的电容实现了频段的调节，通过电压取样和同相放大电路实现了输出电压幅值的调节并提高了电路的带负载能力，可作为频率和幅值可调的方波信号发生器。Multisim 10仿真分析及应用电路测试结果表明，电路性能指标达到了设计要求。 Abstract: Based on Multisim 10， this paper designed a kind of rectangular-wave signal generator which could be controlled exactly composed of operational amplifier， the key point was how to implement and test the parameter indicators based on the circuit diagram. The duty and the frequency were adjusted by changing the time constant and the way of charging and discharging of the capacitor， the width of frequency was adjusted by using different capacitors provided with multiple switch， the amplitude of output voltage was adjusted by sampling voltage and using in-phase amplifier circuit，the ability of driving loads was raised， the circuit can be used as squarewave signal generator whose frequency and amplitude can be adjusted. The final simulation results of Multisim 10 and the tests of applicable circuit show that the performance indicators of the circuit meets the design requirements.
上传时间： 2014-01-21
上传用户：shen007yue
随着总线和接口技术的发展，在工业场合如何更加可靠、快速、便捷地进行数据传输成为该领域通信的研究重点之一。而USB技术以其高速、可靠、通用性强等一系列特点在过去的十多年时间里发展迅猛，而USB OTG技术的诞生，使得两USB设备在没有PC参与的情况下进行数据传输成为可能。本文通过搭建以16位微处理器MSP430F149为核心控制芯片、ISPl362为USB接口芯片的硬件平台，分别实现了USB部分主机和从机功能，使之能进行USB数据的存储与交换。本文完成以下工作：首先，认真研究USB协议，深入理解USB通信的基本概念和传输方式等内容。仔细分析USB Mass Storage类协议，并讨论了采用BULK-ONLY传输实现Mass Storage类协议的方法，并对SCSI指令集等进行了深入的剖析。其次，根据要求，设计出由控制、接口、数据存储、过流保护与供电切换电路等硬件模块组成的系统，在ALTIUM 2004软件上完成原理图的设计和PCB图的布局、布线，并完成硬件调试工作。再次，在已构建的硬件平台上，针对ISPl362 USB接口芯片的主／从机功能，分别设计了USB主机和从机的固件程序。利用IAR Workbench、BusHound等软件进行固件程序的调试，最终USB主机可对u盘进行检测、识别与配置；USB设备实现了USB设备的基本功能，能够被Windows XP操作系统识别，与PC机之间实现数据的批量传输。最后，用DriverWorks软件包的Driver Wizard生成驱动程序框架，并利用Windows DDK和vc++等软件进行驱动程序的编译，最终生成基于Windows操作系统的WDM型USB设备驱动程序。通过对USB通信协议的研究，本人成功地构建了以MsP430F149和ISPl362为核心的硬件试验平台，并在此平台上进行USB主机、从机通信试验。经测试表明，PC机能检测、识别、读写USB设备，其读取与写入速度分别为560KB／s和312Ⅺ玳。而主机能识别、配置接入的U盘。关键词：USB主机、USB从机、MSI'430F149、ISPl362、BuR-Only传输
上传时间： 2013-10-11
上传用户：浅言微笑
Full support for extended regular expressions (those with intersection and complement); Support for some kinds of cycles in grammar; DFA-based operation; Unicode support; C++ only, requires a modern compiler; Lexical analyzers can be configured to get symbols from any input class (built-in support for std::istream, std::wistream and FILE *); Designed to work with Whale, but can work standalone or interface to other parsers.
标签： intersection expressions complement for
上传时间： 2013-12-11
上传用户：zhanditian
工具分类：攻击程序 运行平台：Windows 工具大小：7577 Bytes 文件MD5 ：28f6d5f4d818438522a3d0dc8a3fa46b 工具来源：securiteam.com // GDI+ buffer overrun exploit by FoToZ // NB: the headers here are only sample headers taken from a .JPG file, // with the FF FE 00 01 inserted in header1. // Sample shellcode is provided // You can put approx. 2500 bytes of shellcode...who needs that much anyway // Tested on an unpatched WinXP SP1
标签： 818438522a d818438522 securiteam 818438522
上传时间： 2015-01-20
上传用户：Late_Li
A windows BMP file is a common image format that Java does not handle. While BMP images are used only on windows machines, they are reasonably common. Reading these shows how to read complex structures in Java and how to alter they byte order from the big endian order used by Java to the little endian order used by the windows and the intel processor.
上传时间： 2013-12-27
上传用户：gaojiao1999
What s inside :README - this fileINSTALL - installation instructionsstlport - main STLport include directorysrc - source and makefiles for iostreams implementationlib - installation directory for STLport library (if you use STLport iostreams only)test/regression - regression test, using wrapper iostreamstest/eh - exception handling test using STLport iostreamsetc - miscellanous files (ChangeLog, TODO, scripts, etc.)
标签： instructionsstlport installation fileINSTALL STLport
上传时间： 2014-01-19
上传用户：1159797854
