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multiplication

  • Circular Convolution of two equal-length vectors. Highlights that circular convolution in the time d

    Circular Convolution of two equal-length vectors. Highlights that circular convolution in the time domain is the effectively the same as element-by-element multiplication in the frequency domain.

    标签: equal-length Convolution convolution Highlights

    上传时间: 2014-01-22

    上传用户:aig85

  • Mapack可用来做矩阵运算 Mapack is a .NET class library for basic linear algebra computations. It supports th

    Mapack可用来做矩阵运算 Mapack is a .NET class library for basic linear algebra computations. It supports the following matrix operations and properties: multiplication, Addition, Subtraction, Determinant, Norm1, Norm2, Frobenius Norm, Infinity Norm, Rank, Condition, Trace, Cholesky, LU, QR, Single Value decomposition, Least Squares solver, Eigenproblem solver, Equation System solver. The algorithms were adapted from Mapack for COM, Lapack and the Java Matrix Package.

    标签: Mapack computations supports algebra

    上传时间: 2017-01-26

    上传用户:tb_6877751

  • this code is a implementation of the Discrete cosinuss transformation. In this code I have used the

    this code is a implementation of the Discrete cosinuss transformation. In this code I have used the direct méthode of calcul by used the equation without used the maatrix multiplication.

    标签: this code implementation transformation

    上传时间: 2013-12-19

    上传用户:lanwei

  • 基于FPGA设计的相关论文资料大全 84篇

    基于FPGA设计的相关论文资料大全 84篇用FPGA实现FFT的研究 刘朝晖  韩月秋 摘 要 目的 针对高速数字信号处理的要求,给出了用现场可编程门阵列(FPGA)实现的 快速傅里叶变换(FFT)方案.方法 算法为按时间抽取的基4算法,采用递归结构的块浮点运 算方案,蝶算过程只扩展两个符号位以适应雷达信号处理的特点,乘法器由阵列乘法器实 现.结果 采用流水方式保证系统的速度,使取数据、计算旋转因子、复乘、DFT等操作协 调一致,在计算、通信和存储间取得平衡,避免了瓶颈的出现.结论 实验表明,用FPGA 实现高速数字信号处理的算法是一个可行的方案. 关键词 离散傅里叶变换; 快速傅里叶变换; 块浮点运算; 可编程门阵列 分类号 TP39; TN957.511 Implementation of FFT with FPGA Technology Liu Zhaohui  Han Yueqiu (Department of Electronics Engineering, Beijing Institute of Technology, Beijing 100081) Abstract Aim To propose a scheme for implementing FFT with FPGA in accor-dance with the requirement for high speed digital signal processing. Methods The structure of FPGA and requirement of system were considered in the experiment, radix-4 algorithm of DIT and recursive structure were adopted. The group float point arithmetic operation was used in the butterfly and the array multiplier was used to realize multiplication. Results The pipeline pattern was used to ensure the system speed, it made fetching data, calculating twiddle factor, complex multiplication and D

    标签: fpga

    上传时间: 2022-03-22

    上传用户:lostxc