A multi-hypothesis approach for salient object tracking in visual surveillance
A multi-hypothesis approach for salient object tracking in visual surveillance...
A multi-hypothesis approach for salient object tracking in visual surveillance...
multi uav(多无人机matlab下的仿真)...
Multi interface implementation document for NS-2 for ad hoc network...
Results of the Adaptive Multi-Rate (AMR) noise suppression selection phase...
minimal multi boot source code in assembly . very simple and important....
Verilog-RISC CPU 代码 实现了简单的RISC cpu,可供初学者参考,学习硬件描述语言,及设计方法。该程序通过了modelsim仿真验证。 北航...
连线表: CPU=W78E54B CPUClock=12Mhz * // LCM ----- CPU * // WR ----- WR * // RD ----- RD * // CS ---...
verilog RISC8 cpu CORE 8位RISC CPU 内核源码(VERILOG 版)...
用EPM3128+MEGA8L自制Multi-ICE的全部资料...
·Software Development for Embedded Multi-core Systems...