SAM9261 Basicmmu Example code with ADS1.2 (163 kB) The goal of this project is to show how to use a PC100 SDRAM and the mmu to perform a rating with a 100MHz Bus Clock. The rating is based on Dhrystone 2.1. It shows the rate when I+D Caches are disabled or enabled, with or without mmu and I Cache is disable or enabled, with or without mmu.