本视频主要讲施耐德PLC硬件方面的知识学习，包括Quantum系列的相关模块知识。附件还包括了施耐德PLC联机编程手册。 1 Twido 系列处理器 1.1 使用 USB 口电缆为 Twido 处理器编程 1.1.1 USB 电缆介绍 1.1.2 为 USB 电缆安装驱动 1.1.3 安装 Modbus 驱动 1.1.4 TwidoSoft 软件的设置 1.2 使用串口电缆为 Twido 处理器编程 1.3 Twido 处理器通过集成的以太网口编程 2 Micro 与 Premium 系列 2.1 使用 USB 口电缆为 Micro 与 Premium 处理器编程 2.2 使用串口电缆编程 2.3 使用 XIP 驱动实现 Premium 的以太网编程 2.4 通过 ETZ 以太网模块为 Micro 编程 2.4.1 通过以太网线连接 ETZ 模块 2.4.2 通过串口电缆连接 ETZ 模块 2.4.3 使用 XIP 驱动实现 Micro 的以太网编程 3 M340 系列 3.1 使用 USB 口编程 3.2 使用 Modbus 口编程 3.3 通过以太网实现编程连接 4 Quantum 与 Momentum 系列 4.1 Quantum 使用 USB 口编程 4.2 使用 Modbus 口编程 4.3 通过 Modbus Plus 实现编程连接 4.4 通过以太网实现编程连接
上传时间： 2013-11-21
上传用户：shuizhibai
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
上传时间： 2013-11-01
上传用户：wojiaohs
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2014-11-26
上传用户：erkuizhang
The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).
上传时间： 2013-10-27
上传用户：Breathe0125
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-23
上传用户：shen_dafa
教学提示：可编程序控制器(Programmable Logic Controller,简称PLC)是以微处理器为核心，综合计算机技术、自动控制技术和通信技术发展起来的一种新型工业自动控制装置。随着大规模、超大规模集成电路技术和数字通信技术的进步和发展，PLC技术不断提高，在工业生产中获得极其广泛的应用。教学要求：本章让学生了解PLC及其控制系统的基本知识，重点了解PLC的技术特点、类型以及发展概况。第一章 可编程序控制器概论1.1 PLC的定义及特点1.1.1 PLC的产生及定义1.1.2 PLC的特点1.1.3 PLC的分类1.2 PLC的发展趋势
标签： 可编程序控制器
上传时间： 2013-10-28
上传用户：bnfm
ref-sdr-sdram-vhdl代码 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.
上传时间： 2013-10-23
上传用户：半熟1994
a8259 可编程中断控制 altera提供 The a8259 is designed to simplify the implementation of the interrupt interface in 8088 and 8086 based microcomputer systems. The device is known as a programmable interrupt controller. The a8259 receives and prioritizes up to 8 interrupts, and in the cascade mode, this can be expanded up to 64 interrupts. An asynchronous reset and a clock input have been added to improve operation and reliability.
上传时间： 2015-01-02
上传用户：panpanpan
The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The parallel-processing power， fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control （FOC）。 Additionally， Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID Controller， Clark/Park transforms， and Space Vector PWM. The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control reference designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® Express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-end circuitry.
上传时间： 2013-10-28
上传用户：wujijunshi
CAN（Controller Area Network——控制器局域网）是一种由 CAN 控制器组成的高性能串行数据局域通信网络，是国际上应用最广泛的现场总线之一。它最早由德国 Bosch 公司于 1984 年推出，最初用于汽车内部测量与执行部件之间的数据通信。CAN-bus 总线模型符合 OSI 的 7 层结构；CAN-bus 规范已被 ISO 估计标准组织制定为国际标准。
上传时间： 2013-11-13
上传用户：lvzhr
