搜索结果
找到约 378 项符合
machine 的查询结果
按分类筛选
- 全部分类
- matlab例程 (37)
- 人工智能/神经网络 (32)
- 其他书籍 (27)
- 其他 (24)
- VHDL/FPGA/Verilog (19)
- 书籍 (19)
- 单片机编程 (14)
- 单片机开发 (12)
- 技术资料 (12)
- Java书籍 (11)
- Java编程 (10)
- 电子书籍 (8)
- 数值算法/人工智能 (8)
- 编译器/解释器 (7)
- 可编程逻辑 (6)
- VC书籍 (6)
- Linux/Unix编程 (6)
- 其他嵌入式/单片机内容 (5)
- 数学计算 (5)
- Internet/网络编程 (5)
- 数据结构 (5)
- 操作系统开发 (4)
- 网络 (4)
- 汇编语言 (4)
- 加密解密 (4)
- 文章/文档 (4)
- VIP专区 (4)
- 嵌入式综合 (3)
- 串口编程 (3)
- 编辑器/阅读器 (3)
- 软件设计/软件工程 (3)
- Delphi控件源码 (3)
- 其他行业 (3)
- 行业发展研究 (3)
- 软件工程 (3)
- 模拟电子 (2)
- Mentor (2)
- 教程资料 (2)
- *行业应用 (2)
- 通讯/手机编程 (2)
- Applet (2)
- 嵌入式/单片机编程 (2)
- 数据库系统 (2)
- 系统设计方案 (2)
- Linux/uClinux/Unix编程 (2)
- 图形图像 (2)
- 论文 (2)
- 学术论文 (1)
- 电机控制 (1)
- allegro (1)
- 电源技术 (1)
- 无线通信 (1)
- 开发工具 (1)
- 实用工具 (1)
- 嵌入式Linux (1)
- 中间件编程 (1)
- 压缩解压 (1)
- 多国语言处理 (1)
- Delphi/CppBuilder (1)
- 交通/航空行业 (1)
- 书籍源码 (1)
- TAPI编程 (1)
- JavaScript (1)
- SQL Server (1)
- 微处理器开发 (1)
- 金融证券系统 (1)
- 通讯编程文档 (1)
- 技术管理 (1)
- 文件格式 (1)
- 驱动编程 (1)
- STL (1)
- 技术书籍 (1)
- 接口技术 (1)
- 习题答案 (1)
- 精品软件 (1)
allegro State Machine Coding Styles for Synthesis
 
本文论述了状态机的verilog编码风格,以及不同编码风格的优缺点,Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concernin ...
Mentor Design Safe Verilog State Machine(Synplicity)
 
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability ana ...
可编程逻辑 State Machine Coding Styles for Synthesis
 
本文论述了状态机的verilog编码风格,以及不同编码风格的优缺点,Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concernin ...
可编程逻辑 Design Safe Verilog State Machine(Synplicity)
 
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability ana ...
人工智能/神经网络 Boltzmann Machine Optimization 人工智能人工神经网络源码
Boltzmann Machine Optimization 人工智能人工神经网络源码
编译器/解释器 Tiny Machine的源码
Tiny Machine的源码,一个简单易学习的
VHDL/FPGA/Verilog State.Machine.Coding.Styles.for.Synthesis(状态机
State.Machine.Coding.Styles.for.Synthesis(状态机,英文,VHDL)
电子书籍 machine learning
machine learning
*行业应用 surpport vector machine,matlab
surpport vector machine,matlab
其他 JILRuntime A general purpose, register based virtual machine (VM) that supports object-oriented feat
JILRuntime A general purpose, register based virtual machine (VM) that supports object-oriented features, reference counting (auto destruction of data as soon as it is no longer used, no garbage collection), exceptions (handled in C/C++ or virtual machine code) and other debugging features. Objects ...