自己做的vhdl课程设计，交通灯：实现主干道倒计时，分别为30,20,5秒，分情况：当主干道有车时，红黄绿交替，当只一个道路上有车时，那个道的交通灯变绿色，利用max+plus2做成，使用flex8000,epf8282alc84_4只用加一个38译码器模块即可，使用别的板子也可以运行
标签： vhdl
上传时间： 2017-02-03
上传用户：努力努力再努力
c++语言程序设计超级简单了解，你会惊喜地发现你可以后人乘凉：max是C++标准库的一部分。
上传时间： 2013-12-15
上传用户：啊飒飒大师的
Description The art galleries of the new and very futuristic building of the Center for Balkan Cooperation have the form of polygons (not necessarily convex). When a big exhibition is organized, watching over all of the pictures is a big security concern. Your task is that for a given gallery to write a program which finds the surface of the area of the floor, from which each point on the walls of the gallery is visible. On the figure 1. a map of a gallery is given in some co-ordinate system. The area wanted is shaded on the figure 2.
标签： Description futuristic galleries the
上传时间： 2017-02-17
上传用户：1427796291
Input : A set S of planar points Output : A convex hull for S Step 1: If S contains no more than five points, use exhaustive searching to find the convex hull and return. Step 2: Find a median line perpendicular to the X-axis which divides S into SL and SR SL lies to the left of SR . Step 3: Recursively construct convex hulls for SL and SR. Denote these convex hulls by Hull(SL) and Hull(SR) respectively. Step 4: Apply the merging procedure to merge Hull(SL) and Hull(SR) together to form a convex hull. Time complexity: T(n) = 2T(n/2) + O(n) = O(n log n)
标签： contains Output convex planar
上传时间： 2017-02-19
上传用户：wyc199288
Instead of finding the longest common subsequence, let us try to determine the length of the LCS. Then tracking back to find the LCS. Consider a1a2…am and b1b2…bn. Case 1: am=bn. The LCS must contain am, we have to find the LCS of a1a2…am-1 and b1b2…bn-1. Case 2: am≠bn. Wehave to find the LCS of a1a2…am-1 and b1b2…bn, and a1a2…am and b b b b1b2…bn-1 Let A = a1 a2 … am and B = b1 b2 … bn Let Li j denote the length of the longest i,g g common subsequence of a1 a2 … ai and b1 b2 … bj. Li,j = Li-1,j-1 + 1 if ai=bj max{ L L } a≠b i-1,j, i,j-1 if ai≠j L0,0 = L0,j = Li,0 = 0 for 1≤i≤m, 1≤j≤n.
标签： the subsequence determine Instead
上传时间： 2013-12-17
上传用户：evil
4位电子智能密码锁，基于VHDL语言设计，MAX+PLUSⅡ环境下实现
上传时间： 2013-11-30
上传用户：athjac
1. socket通信：有客户端和服务端的socket代码。 2. 多线程：客户端和服务端各用一线程发送信息；服务端另有一监听线程，用于把超时的信息删除。 这里应用到了同步，使两个线程可以操作同一个map。
上传时间： 2017-02-27
上传用户：lanwei
cordic methods describe essentially the same algorithm that with suitably chosen inputs can be used to calculate a whole range of scientific functions including sin, cos, tan, arctan, arcsin, arccos, sinh, cosh, tanh, arctanh, log, exp, square root and even multiply and divide. the method dates back to volder [1959], and due to its versatility and compactness, it made possible the microcoding of the hp35 pocket scientific calculator in 1972. here is some code to illustrate the techniques. ive split the methods into three parts linear, circular and hyperbolic. in the hp35 microcode these would be unified into one function (for space reasons). because the linear mode can perform multiply and divide, you only need add/subtract and shift to complete the implementation. you can select in the code whether to do the multiples and divides also by cordic means. other multiplies and divides are all powers of 2 (these dont count). to eliminate these too, would involve ieee hackery.
标签： essentially algorithm describe suitably
上传时间： 2017-03-02
上传用户：litianchu
Verilog HDL的程式，上網找到SPI程式， vspi.v這程式相當好用可用來接收與傳送SPI，並且寫了一個傳輸信號測試，spidatasent.v這程式就是傳送的資料，分別為00 66... 01 77...... 02 55這樣的資料，並透過MAX+PULS II軟體進行模擬，而最外層的程式是test_createspi.v！
上传时间： 2017-03-06
上传用户：onewq
Verilog是广泛应用的硬件描述语言，可以用在硬件设计流程的建模、综合和模拟等多个阶段。随着硬件设计规模的不断扩大，应用硬件描述语言进行描述的CPLD结构，成为设计专用集成电路和其他集成电路的主流。通过应用Verilog HDL对多功能电子钟的设计，达到对Verilog HDL的理解，同时对CPLD器件进行简要了解。 本文的研究内容包括: 对Altera公司Flex 10K系列的EPF10K 10简要介绍，Altera公司软件Max+plusⅡ简要介绍和应用Verilog HDL对多功能电子钟进行设计。
上传时间： 2017-03-06
上传用户：epson850
