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lin-BUS

  • 采用双核处理器OMAP3530的嵌入式工控机主板

    EPCS-9000 提供了一路CAN-bus现场总线接口和一个摄像头接口。可以在工业温度范围(-40℃~85℃)内稳定工作,可以满足各种条件苛刻的工业应用,如:工业控制、现场通信、远程监控等领域;也可以满足一般的多媒体应用,如:视频监控、视频广告等领域。

    标签: OMAP 3530 双核处理器 嵌入式

    上传时间: 2013-10-11

    上传用户:kao21

  • 8051单片机系统扩展与接口技术

    8051单片机系统扩展与接口技术:第一节   8051 单片机系统扩展概述第二节  单片机外部存储器扩展第三节  单片机输入输出(I/O)口扩展及应用第四节   LED显示器接口电路及显示程序第五节  单片机键盘接口技术第六节 单片机与数模(D/A)及模数(A/D)转换1、地址总线(Address Bus,简写为AB)地址总线可传送单片机送出的地址信号,用于访问外部存储器单元或I/O端口。A   地址总线是单向的,地址信号只是由单片机向外发出。B   地址总线的数目决定了可直接访问的存储器单元的数目。例如N位地址,可以产生2N个连续地址编码,因此可访问2N个存储单元,即通常所说的寻址范围为 2N个地址单元。MCS—51单片机有十六位地址线,因此存储器展范围可达216 = 64KB地址单元。C   挂在总线上的器件,只有地址被选中的单元才能与CPU交换数据,其余的都暂时不能操作,否则会引起数据冲突。2、数据总线(Data Bus,简写为DB)数据总线用于在单片机与存储器之间或单片机与I/O端口之间传送数据。A   单片机系统数据总线的位数与单片机处理数据的字长一致。例如MCS—51单片机是8位字长,所以数据总线的位数也是8位。B   数据总线是双向的,即可以进行两个方向的数据传送。3、控制总线(Control Bus,简写为CB)控制总线实际上就是一组控制信号线,包括单片机发出的,以及从其它部件送给单片机的各种控制或联络信号。对于一条控制信号线来说,其传送方向是单向的,但是由不同方向的控制信号线组合的控制总线则表示为双向的。总线结构形式大大减少了单片机系统中连接线的数目,提高了系统的可靠性,增加了系统的灵活性。此外,总线结构也使扩展易于实现,各功能部件只要符合总线规范,就可以很方便地接入系统,实现单片机扩展。

    标签: 8051 单片机 系统扩展 接口技术

    上传时间: 2013-10-18

    上传用户:assef

  • 基于8086 CPU 的单芯片计算机系统的设计

    本文依据集成电路设计方法学,探讨了一种基于标准Intel 8086 微处理器的单芯片计算机平台的架构。研究了其与SDRAM,8255 并行接口等外围IP 的集成,并在对AMBA协议和8086 CPU分析的基础上,采用遵从AMBA传输协议的系统总线代替传统的8086 CPU三总线结构,搭建了基于8086 IP 软核的单芯片计算机系统,并实现了FPGA 功能演示。关键词:微处理器; SoC;单芯片计算机;AMBA 协议 Design of 8086 CPU Based Computer-on-a-chip System(School of Electrical Engineering and Automation, Heifei University of Technology, Hefei, 230009,China)Abstract: According to the IC design methodology, this paper discusses the design of one kind of Computer-on-a-chip system architecture, which is based on the standard Intel8086 microprocessor,investigates how to integrate the 8086 CPU and peripheral IP such as, SDRAM controller, 8255 PPI etc. Based on the analysis of the standard Intel8086 microprocessor and AMBA Specification,the Computer-on-a-chip system based on 8086 CPU which uses AMBA bus instead of traditional three-bus structure of 8086 CPU is constructed, and the FPGA hardware emulation is fulfilled.Key words: Microprocessor; SoC; Computer-on-a-chip; AMBA Specification

    标签: 8086 CPU 单芯片 计算机系统

    上传时间: 2013-12-27

    上传用户:kernor

  • 多功能高集成外围器件

     多功能高集成外围器件6. 1  多功能高集成外围器件82371PCI的英文名称:Peripheral Component Interconnect (外围部件互联PCI总线);82371是PCI总线组件。ISA是:Industry Standard Architecture(工业标准体系结构)IDE是 (Integrated Device Electronics)集成电路设备简称PIIX4PIIX4器件(芯片)的特点1、是一种支持Pentium和PentiumII微处理器的部件。2、82371对ISA桥来说,是一种多功能PCI总线。3、对可移动性和桌面深绿色环境均提供支持。4、电源管理逻辑。5、被集成化的IDE控制器。6、增强了性能的DMA控制器。 (7)基于两个82C59的中断控制器。(8)基于82C54芯片的定时器。(9)USB(Universal Serial Bus)通用串行总线。(10)SMBus系统管理总线。(11)实时时钟(12)顺应Microsoft Win95所需的功能其芯片的逻辑框图如图6-1所示。    PIIX4芯片逻辑框图6.1.1   概述PIIX4芯片是一个多功能的PCI器件,图6-2 是82371在系统中扮演的角色。(续上图)1. PCI与EIO之间的桥(PIIX4芯片)桥是不对程的,是各类不同标准总线与PCI总线连接,82371AB桥也可理解为一种总线转换译码器和控制器,桥内包含复杂的协议总线信号和缓冲器。(1).在PCI系统内,当PIIX4操作时,它总是作为系统内各种模块的主控设备,如USB和DMA控制器、IDE总线和分布式DMA的主控设备等,而且总是以ISA主控设备的名义出现。(2).  在向ISA总线或IDE总线进行传送操作的传送周期期间作为从属设备使用,并对内部寄存器译码。PIIX4芯片(桥)的配置(1).可以把PIIX4芯片配置成整个ISA总线,或ISA总线的子集,也可扩展成EIO总线。在使用EIO总线时,可以把未使用的信号配置成通用的输入和输出。(2).PIIX4可直接驱动5个ISA插槽;(3).能提供字节-交换逻辑、I/O的恢复支持、等待状态的生成以及SYSCLK的生成。(4).提供X-BUS键盘控制器芯片、BIOS芯片、实时时钟芯片、二级微程序器等的选择。2.  IDE接口(总线主控设备的权利和同步DMA方式)IDE接口为4个IDE的设备提供支持,比如IDE接口的硬盘和CD-ROM等。注意:目前硬盘接口有5类:IDE、SCSI、Fibre Channel、IEEE1394和USB等。IDE口几乎在PC机最多,因为便宜。SCSI多用于服务器和集群机。IDE的PIO IDE速率:14MB/s;而总线主控设备IDE的速率:33MB/s在PIIX4芯片的IDE系统内,配有两个各次独立的IDE信号通道。3. 具有兼容性的模块—DMA、定时器/计数器、中断控制器等(1)在PIIX4内的两各82C37 DMA控制器经逻辑的组合,产生7个独立的可编程通道。通道[0:3]是通过与8个二进位的硬件连线实现的。通过以字节为单位的计数进行传送。而通道[5:7]是通过16个二进位的连线实现的,以字为单位的计数进行传送。(2)DMA控制器还能通过PCI总线,处理旧的DMA的两个不同的方法提供支持。(3)计数/定时器模块在功能上与82C54等价。(4)中断控制器与ISA兼容,其功能是两个82C59的功能之和。

    标签: 多功能 外围器件 集成

    上传时间: 2013-11-19

    上传用户:3到15

  • 51单片机工程师实例设计程序集-(20种常见应用整编)

    51单片机工程师实例设计程序集-(20种常见应用整编) \7290\                          ;ZLG7290例程*\7290a\                         ;ZLG7290汇编例程*\bell\                          ;蜂鸣器音乐例程*\buzz\                          ;蜂鸣器响例程*\eeprom\                        ;读EEPROM并显示例程*\ex26a_lcd\                     ;16×2LCD模块例程*\ex36a_lcm\                     ;128×64点阵LCD模块例程*\KEY_IO\                        ;直连KEY和LED例程\led_light\                     ;直连LED例程*\lin_park\   ;lin模块的原码及例程。\lin\                           ;LIN总线例程\rs232\                         ;RS232例程(包括PC端和书上了串口例程)\USB1.1\                        ;USB1.1例程(包括PC端)\RS485\                         ;RS485例程\USB2.0\                        ;USB2.0例程(有3个,包括PC端)\TCPIP\                         ;基于ETHERNET的TCPIP例程\RTC\                           ;时钟显示例程\CAN_SELF\                      ;CAN自发自收例程  外中断1\CAN\                           ;CAN例程\USBPACK 2.0\                   ;USB2.0PC例程 注意:带*程序为MON51调试程序。在MON时程序下载后停不下来,可以按一下RSE按钮复位一下。

    标签: 51单片机 工程师 设计程序

    上传时间: 2013-10-13

    上传用户:雨出惊人love

  • MPC106 PCI Bridge/Memory Contr

    In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.

    标签: Bridge Memory Contr MPC

    上传时间: 2013-10-08

    上传用户:18711024007

  • MPC106 PCI桥/存储器控制器硬件规范说明

    The Motorola MPC106 PCI bridge/memory controller provides a PowerPCªmicroprocessor common hardware reference platform (CHRPª) compliant bridgebetween the PowerPC microprocessor family and the Peripheral Component Interconnect(PCI) bus. In this document, the term Ô106Õ is used as an abbreviation for the phraseÔMPC106 PCI bridge/memory controllerÕ. This document contains pertinent physicalcharacteristics of the 106. For functional characteristics refer to theMPC106 PCI Bridge/Memory Controller UserÕs Manual.This document contains the following topics:Topic PageSection 1.1, ÒOverviewÓ 2Section 1.2, ÒFeaturesÓ 3Section 1.3, ÒGeneral ParametersÓ 5Section 1.4, ÒElectrical and Thermal CharacteristicsÓ 5Section 1.5, ÒPin AssignmentsÓ 17Section 1.6, ÒPinout Listings 18Section 1.7, ÒPackage DescriptionÓ 22Section 1.8, ÒSystem Design InformationÓ 24Section 1.9, ÒDocument Revision HistoryÓ 29Section 1.10, ÒOrdering InformationÓ 29

    标签: MPC 106 PCI 存储器

    上传时间: 2013-11-04

    上传用户:as275944189

  • USB Demonstration for DK3200 w

    The μPSD32xx family, from ST, consists of Flash programmable system devices with a 8032 MicrocontrollerCore. Of these, the μPSD3234A and μPSD3254A are notable for having a complete implementationof the USB hardware directly on the chip, complying with the Universal Serial Bus Specification, Revision1.1.This application note describes a demonstration program that has been written for the DK3200 hardwaredemonstration kit (incorporating a μPSD3234A device). It gives the user an idea of how simple it is to workwith the device, using the HID class as a ready-made device driver for the USB connection.IN-APPLICATION-PROGRAMMING (IAP) AND IN-SYSTEM-PROGRAMMING (ISP)Since the μPSD contains two independent Flash memory arrays, the Micro Controller Unit (MCU) can executecode from one memory while erasing and programming the other. Product firmware updates in thefield can be reliably performed over any communication channel (such as CAN, Ethernet, UART, J1850)using this unique architecture. For In-Application-Programming (IAP), all code is updated through theMCU. The main advantage for the user is that the firmware can be updated remotely. The target applicationruns and takes care on its own program code and data memory.IAP is not the only method to program the firmware in μPSD devices. They can also be programmed usingIn-System-Programming (ISP). A IEEE1149.1-compliant JTAG interface is included on the μPSD. Withthis, the entire device can be rapidly programmed while soldered to the circuit board (Main Flash memory,Secondary Boot Flash memory, the PLD, and all configuration areas). This requires no MCU participation.The MCU is completely bypassed. So, the μPSD can be programmed or reprogrammed any time, anywhere, even when completely uncommitted.Both methods take place with the device in its normal hardware environment, soldered to a printed circuitboard. The IAP method cannot be used without previous use of ISP, because IAP utilizes a small amountof resident code to receive the service commands, and to perform the desired operations.

    标签: Demonstration 3200 USB for

    上传时间: 2014-02-27

    上传用户:zhangzhenyu

  • 对带有uPSD3234A的DK3200的USB演示

    The μPSD32xx family, from ST, consists of Flash programmable system devices with a 8032 Microcontroller Core. Of these, the μPSD3234A and μPSD3254A are notable for having a complete implementation of the USB hardware directly on the chip, complying with the Universal Serial Bus Specification, Revision 1.1.This application note describes a demonstration program that has been written for the DK3200 hardware demonstration kit (incorporating a μPSD3234A device). It gives the user an idea of how simple it is to work with the device, using the HID class as a ready-made device driver for the USB connection.

    标签: 3234A uPSD 3234 3200

    上传时间: 2014-04-03

    上传用户:lizhizheng88

  • An easy way to work with Exter

    Internal Interrupts are used to respond to asynchronous requests from a certain part of themicrocontroller that needs to be serviced. Each peripheral in the TriCore as well as theBus Control Unit, the Debug Unit, the Peripheral Control Processor (PCP) and the CPUitself can generate an Interrupt Request.So what is an external Interrupt?An external Interrupt is something alike as the internal Interrupt. The difference is that anexternal Interrupt request is caused by an external event. Normally this would be a pulseon Port0 or Port1, but it can be even a signal from the input buffer of the SSC, indicatingthat a service is requested.The User’s Manual does not explain this aspect in detail so this ApNote will explain themost common form of an external Interrupt request. This ApNote will show that there is aneasy way to react on a pulse on Port0 or Port1 and to create with this impulse an InterruptService Request. Later in the second part of the document, you can find hints on how todebounce impulses to enable the use of a simple switch as the input device.Note: You will find additional information on how to setup the Interrupt System in theApNote “First steps through the TriCore Interrupt System” (AP3222xx)1. It would gobeyond the scope of this document to explain this here, but you will find selfexplanatoryexamples later on.

    标签: Exter easy work with

    上传时间: 2013-10-27

    上传用户:zhangyigenius