搜索：latched
找到约 7 项符合「latched」的查询结果
结果 7
https://www.eeworm.com/dl/687/459507.html
其他嵌入式/单片机内容
Event counter for MSP430 - multi channel and real fast using latched interrupts.
Event counter for MSP430 - multi channel and real fast using latched interrupts.
https://www.eeworm.com/dl/930530.html
技术资料
4515 CMOS四位锁存、4-16低有效译码器
The CD4514BC and CD4515BC are 4-to-16 line decoderswith latched inputs implemented with compleme
https://www.eeworm.com/dl/924083.html
技术资料
4514 CMOS 四位锁存、4-16高有效译码器
The CD4514BC and CD4515BC are 4-to-16 line decoderswith latched inputs implemented with compl
https://www.eeworm.com/dl/516/385120.html
DSP编程
The SL74HC573 is identical in pinout to the LS/ALS573. The device inputs are compatible with standa
The SL74HC573 is identical in pinout to the LS/ALS573. The device
inputs are compatible with standard CMOS outputs with pullup
resistors, they are compatible with LS/ALSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enab ...
https://www.eeworm.com/dl/663/292193.html
VHDL/FPGA/Verilog
vhdl编写
vhdl编写，8b—10b 编解码器设计
Encoder:
8b/10b Encoder (file: 8b10b_enc.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
8-bit parallel unencoded data input
KI input selects data or control encoding
Asynchronous active high reset initializes all logic
E ...
https://www.eeworm.com/dl/663/361747.html
VHDL/FPGA/Verilog
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shi ...
https://www.eeworm.com/dl/663/361749.html
VHDL/FPGA/Verilog
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shi ...