代码搜索：latched
找到约 88 项符合「latched」的源代码
代码结果 88
www.eeworm.com/read/258643/11848456
v latched_seven_seg_display.v
module Latched_Seven_Seg_Display
(Display_L, Display_R, Blanking, Enable, clock, reset);
output [6: 0] Display_L, Display_R;
input Blanking, Enable, clock, reset;
reg [6: 0] Display_L,
www.eeworm.com/read/258643/11848599
v latched_seven_seg_display.v
vti_encoding:SR|utf8-nl
vti_timelastmodified:TR|12 Jun 2002 17:27:32 -0000
vti_extenderversion:SR|5.0.2.4330
vti_lineageid:SR|{F1C64FC7-C79D-4222-B200-DDECADEC41D3}
vti_cacheddtm:TX|12 Jun 2002 17
www.eeworm.com/read/463239/1538823
v latched_seven_seg_display.v
module Latched_Seven_Seg_Display
(Display_L, Display_R, Blanking, Enable, clock, reset);
output [6: 0] Display_L, Display_R;
input Blanking, Enable, clock, reset;
reg [6: 0] Display_L,
www.eeworm.com/read/463239/1538862
v latched_seven_seg_display.v
vti_encoding:SR|utf8-nl
vti_timelastmodified:TR|12 Jun 2002 17:27:32 -0000
vti_extenderversion:SR|5.0.2.4330
vti_lineageid:SR|{F1C64FC7-C79D-4222-B200-DDECADEC41D3}
vti_cacheddtm:TX|12 Jun 2002 17
www.eeworm.com/read/268818/4249807
v latched_seven_seg_display.v
module Latched_Seven_Seg_Display
(Display_L, Display_R, Blanking, Enable, clock, reset);
output [6: 0] Display_L, Display_R;
input Blanking, Enable, clock, reset;
reg [6: 0] Display_L,
www.eeworm.com/read/268818/4249846
v latched_seven_seg_display.v
vti_encoding:SR|utf8-nl
vti_timelastmodified:TR|12 Jun 2002 17:27:32 -0000
vti_extenderversion:SR|5.0.2.4330
vti_lineageid:SR|{F1C64FC7-C79D-4222-B200-DDECADEC41D3}
vti_cacheddtm:TX|12 Jun 2002 17
www.eeworm.com/read/172784/9690547
v sci_alu_latched_shell.v
/**********************************************************************
* $scientific_alu example -- Verilog HDL shell module
*
* Scientific ALU C model, latched logic version.
*
* Note: The
www.eeworm.com/read/172784/9690563
v sci_alu_latched_test.v
/**********************************************************************
* $scientific_alu example -- Verilog HDL test bench.
*
* Verilog test bench to test the $scientific_alu C model PLI
* a
www.eeworm.com/read/172784/9690565
c sci_alu_latched_acc.c
/**********************************************************************
* $scientific_alu example -- PLI application using TF routines
*
* C model of a Scientific Arithmetic Logic Unit.
* la
www.eeworm.com/read/172784/9690578
log sci_alu_latched_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
sci_alu_latched_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Jan 12, 1999 11:44:22
Verilog_XL_Turbo_NT 2.6.9 Ja