(1) 、用下述两条具体规则和规则形式实现.设大写字母表示魔王语言的词汇 小写字母表示人的语言词汇 希腊字母表示可以用大写字母或小写字母代换的变量.魔王语言可含人的词汇. (2) 、B→tAdA A→sae (3) 、将魔王语言B(ehnxgz)B解释成人的语言.每个字母对应下列的语言.
上传时间： 2013-12-30
上传用户：ayfeixiao
1.有三根杆子A,B,C。A杆上有若干碟子 2.每次移动一块碟子,小的只能叠在大的上面 3.把所有碟子从A杆全部移到C杆上 经过研究发现，汉诺塔的破解很简单，就是按照移动规则向一个方向移动金片： 如3阶汉诺塔的移动：A→C,A→B,C→B,A→C,B→A,B→C,A→C 此外，汉诺塔问题也是程序设计中的经典递归问题
上传时间： 2016-07-25
上传用户：gxrui1991
1. 下列说法正确的是 （ ） A. Java语言不区分大小写 B. Java程序以类为基本单位 C. JVM为Java虚拟机JVM的英文缩写 D. 运行Java程序需要先安装JDK 2. 下列说法中错误的是 ( ) A. Java语言是编译执行的 B. Java中使用了多进程技术 C. Java的单行注视以//开头 D. Java语言具有很高的安全性 3. 下面不属于Java语言特点的一项是( ) A. 安全性 B. 分布式 C. 移植性 D. 编译执行 4. 下列语句中，正确的项是 ( ) A . int $e,a,b=10 B. char c,d=’a’ C. float e=0.0d D. double c=0.0f
上传时间： 2017-01-04
上传用户：netwolf
TLC2543是TI公司的12位串行模数转换器，使用开关电容逐次逼近技术完成A/D转换过程。由于是串行输入结构，能够节省51系列单片机I/O资源；且价格适中，分辨率较高，因此在仪器仪表中有较为广泛的应用。 TLC2543的特点 （1）12位分辩率A/D转换器； （2）在工作温度范围内10μs转换时间； （3）11个模拟输入通道； （4）3路内置自测试方式； （5）采样率为66kbps； （6）线性误差±1LSBmax； （7）有转换结束输出EOC； （8）具有单、双极性输出； （9）可编程的MSB或LSB前导； （10）可编程输出数据长度。 TLC2543的引脚排列及说明 TLC2543有两种封装形式：DB、DW或N封装以及FN封装，这两种封装的引脚排列如图1，引脚说明见表1 TLC2543电路图和程序欣赏 #include<reg52.h> #include<intrins.h> #define uchar unsigned char #define uint unsigned int sbit clock=P1^0; sbit d_in=P1^1; sbit d_out=P1^2; sbit _cs=P1^3; uchar a1,b1,c1,d1; float sum,sum1; double sum_final1; double sum_final; uchar duan[]={0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f}; uchar wei[]={0xf7,0xfb,0xfd,0xfe}; void delay(unsigned char b) //50us { unsigned char a; for(;b>0;b--) for(a=22;a>0;a--); } void display(uchar a,uchar b,uchar c,uchar d) { P0=duan[a]|0x80; P2=wei[0]; delay(5); P2=0xff; P0=duan[b]; P2=wei[1]; delay(5); P2=0xff; P0=duan[c]; P2=wei[2]; delay(5); P2=0xff; P0=duan[d]; P2=wei[3]; delay(5); P2=0xff; } uint read(uchar port) { uchar i,al=0,ah=0; unsigned long ad; clock=0; _cs=0; port<<=4; for(i=0;i<4;i++) { d_in=port&0x80; clock=1; clock=0; port<<=1; } d_in=0; for(i=0;i<8;i++) { clock=1; clock=0; } _cs=1; delay(5); _cs=0; for(i=0;i<4;i++) { clock=1; ah<<=1; if(d_out)ah|=0x01; clock=0; } for(i=0;i<8;i++) { clock=1; al<<=1; if(d_out) al|=0x01; clock=0; } _cs=1; ad=(uint)ah; ad<<=8; ad|=al; return(ad); } void main() { uchar j; sum=0;sum1=0; sum_final=0; sum_final1=0; while(1) { for(j=0;j<128;j++) { sum1+=read(1); display(a1,b1,c1,d1); } sum=sum1/128; sum1=0; sum_final1=(sum/4095)*5; sum_final=sum_final1*1000; a1=(int)sum_final/1000; b1=(int)sum_final%1000/100; c1=(int)sum_final%1000%100/10; d1=(int)sum_final%10; display(a1,b1,c1,d1); } }
上传时间： 2013-11-19
上传用户：shen1230
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上传时间： 2013-10-23
上传用户：copu
PCB LAYOUT技术大全---初学者必看！ PROTEL相关疑问 1.原理图常见错误： （1）ERC报告管脚没有接入信号： a. 创建封装时给管脚定义了I/O属性; b.创建元件或放置元件时修改了不一致的grid属性,管脚与线没有连上; c. 创建元件时pin方向反向,必须非pin name端连线。 （2）元件跑到图纸界外：没有在元件库图表纸中心创建元件。 （3）创建的工程文件网络表只能部分调入pcb：生成netlist时没有选择为global。 （4）当使用自己创建的多部分组成的元件时,千万不要使用annotate. 2.PCB中常见错误： （1）网络载入时报告NODE没有找到： a. 原理图中的元件使用了pcb库中没有的封装; b. 原理图中的元件使用了pcb库中名称不一致的封装; c. 原理图中的元件使用了pcb库中pin number不一致的封装。如三极管：sch中pin number 为e,b,c, 而pcb中为1,2,3。
上传时间： 2013-10-20
上传用户：kbnswdifs
数字运算，判断一个数是否接近素数 A Niven number is a number such that the sum of its digits divides itself. For example, 111 is a Niven number because the sum of its digits is 3, which divides 111. We can also specify a number in another base b, and a number in base b is a Niven number if the sum of its digits divides its value. Given b (2 <= b <= 10) and a number in base b, determine whether it is a Niven number or not. Input Each line of input contains the base b, followed by a string of digits representing a positive integer in that base. There are no leading zeroes. The input is terminated by a line consisting of 0 alone. Output For each case, print "yes" on a line if the given number is a Niven number, and "no" otherwise. Sample Input 10 111 2 110 10 123 6 1000 8 2314 0 Sample Output yes yes no yes no
上传时间： 2015-05-21
上传用户：daguda
高精度乘法基本思想和加法一样。其基本流程如下： ①读入被乘数s1，乘数s2 ②把s1、s2分成4位一段，转成数值存在数组a,b中；记下a,b的长度k1,k2； ③i赋为b中的最低位； ④从b中取出第i位与a相乘，累加到另一数组c中；（注意：累加时错开的位数应是多少位 ？） ⑤i:=i-1；检测i值：小于k2则转⑥,否则转④ ⑥打印结果
上传时间： 2015-08-16
上传用户：源弋弋
I have a dream that I am always young. Then I will have enough energy to do everything whenever I want. Moreover, I don t have to worry about the old age during which I even can t take care of myself
标签： have everything whenever always
上传时间： 2016-01-24
上传用户：whenfly
The XML Toolbox converts MATLAB data types (such as double, char, struct, complex, sparse, logical) of any level of nesting to XML format and vice versa. For example, >> project.name = MyProject >> project.id = 1234 >> project.param.a = 3.1415 >> project.param.b = 42 becomes with str=xml_format(project, off ) "<project> <name>MyProject</name> <id>1234</id> <param> <a>3.1415</a> <b>42</b> </param> </project>" On the other hand, if an XML string XStr is given, this can be converted easily to a MATLAB data type or structure V with the command V=xml_parse(XStr).
标签： converts Toolbox complex logical
上传时间： 2016-02-12
上传用户：a673761058
