在汽车发动机起动时，若发动机起动后起动机不能及时断电，将会烧毁起动机或损坏飞轮齿环；若变速器不在空档位置起动，则起动机的瞬间动力将使汽车位移，还可能引起交通事故和人身安全。为此介绍一种利用NXP P89LPC901单片机控制的汽车起动保护控制器，通过检测汽车起动开关、变速箱档位、发动机转速，实现对汽车发动机起动过程检测和保护。起动保护控制器在发动机起动过程中通过采用逐个关闭打开负载系统，解决汽车发动机过程中因起动电流大而对汽车电源的冲击影响,延长了电瓶寿命。 Abstract: When the automotive engine is started, the engine start motor and flywheel gear may be damaged， even traffic accidents and personal safeties may be caused by wrong operation or other factors.In order to ensure the automotive engine can be started normally and safely,it is necessary that the protecting measures and methods are considered in the automotive electrical control system.This paper introduces a kind of the automotive engine starting protect controller based on NXP P89LPC901 MCU.The controller can protect the engine starting process by detecting the starter key switch,transmission stall and engine speed.Through the use of close and open load system,the controller can solve the impact on automotive power because of the high-current load in the process of the automobile engine starting, and extend battery life.
上传时间： 2013-10-15
上传用户：mikesering
针对当前安检力学试验机所能完成的试验种类单一、自动化程度低等问题，提出一种以ATmega128单片机为核心控制器的安检力学试验机的设计。详细阐述了该安检力学试验机各个组成部分的设计原理和方案，并且给出了各部分的软件设计思想和操作流程。经过大量测试试验表明：设计的安检力学试验机可以完成多达十余种的力学安检试验，完全符合相关国家标准，并且具有数据采集精度高、传输速度快、操作安全简便等特点，实现了安检设备的多功能化、数字化和自动化。 Abstract: Currently， many mechanical security testing machines have only one function. The degree of automation of them is low. To solve those problems， a new kind of mechanical security testing machine， using ATmega128 micro-controller as its core controller， has been advanced. It describes the components of the machine. The principles and the scheme in the designing processes are presented in detail， and the software architecture and the operation processes of each part are given. After having done many testing， we have reached the following conclusions: the mechanical security testing machine presented can do over ten mechanical security tests complying with related national standards. It has high data acquisition accuracy and high transmission speed. The operation of the machine is simple and safe. In general， this machine is a multi-functional， highly automatic， digitalized security testing device.
上传时间： 2013-11-05
上传用户：a67818601
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
Libnet is a cross-platform library aimed at game developers. It has an abstract high level API, which encourages developers to make their games portable across platforms and network types
标签： cross-platform developers abstract library
上传时间： 2015-01-14
上传用户：ghostparker
High Performance MySQL (O Reilly,2004）
标签： Performance Reilly MySQL High
上传时间： 2015-02-21
上传用户：nanfeicui
NTL is a high-performance, portable C++ library providing data structures and algorithms for manipulating signed, arbitrary length integers, and for vectors, matrices, and polynomials over the integers and over finite fields.
标签： high-performance algorithms structures providing
上传时间： 2014-01-05
上传用户：水中浮云
SR-tree is an index structure for high-dimensional nearest neighbor queries，C++ sourcecode. SR-tree outperforms the R*-tree and the SS-tree especially for high-dimensional and non-uniform data which are likely to appear in the actual image / video applications.
标签： high-dimensional structure neighbor SR-tree
上传时间： 2013-12-10
上传用户：zjf3110
A high quality VC++ source code implementing the very important context-based adaptive arithmetic coder.
标签： context-based implementing arithmetic important
上传时间： 2015-04-10
上传用户：changeboy
Control of High Voltage 3-Phase BLDC Motor
标签： Control Voltage Phase Motor
上传时间： 2015-04-21
上传用户：silenthink
