众所周知在非 Admin 用户模式下，是不允许加载驱动执行 RING 0 代码的。 本文提供了一种方法，通过修改系统 GDT，IDT 来添加自己的 CALLgate 和 INTgate 这样便在系统中设置了一个后门。我们就可以利用这个后门 在任意用户模式下执行 ring 0 代码了。为了保证我们添加的 CALLgate 和 INT gate 永久性。可以在第一次安装时利用 SERVICE API 或 INF 文件设置成随 系统启动。不过此方法也有个缺陷，就是在第一次安装 CALLgate 或 INTgate 时仍然需要 ADMIN 权限。下面分别给出了添加 CALLgate 与 INTgate 的具体 代码。
上传时间： 2016-02-14
上传用户：chongcongying
TFT6758液晶模块驱动。(头文件) 驱动芯片为HD66781 (片内224640字节GRAM,即240*(96+320)*18/8)，门驱动(gate driver)芯片为HD66783
上传时间： 2014-12-01
上传用户：1101055045
The SST89E516RDx and SST89V516RDx are members of the FlashFlex51 family of 8-bit microcontroller products designed and manufactured with SST’s patented and proprietary SuperFlash CMOS semiconductor process technology. The split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for SST’s customers. The devices use the 8051 instruction set and are pin-for-pin compatible with standard 8051 microcontroller devices.
标签： microcontroller SST 516 RDx
上传时间： 2014-01-07
上传用户：笨小孩
ili9320 datasheet. ILI9320 is a 262,144-color one-chip SoC driver for a-TFT liquid crystal display with resolution of 240RGBx320 dots, comprising a 720-channel source driver, a 320-channel gate driver, 172,800 bytes RAM for graphic data of 240RGBx320 dots, and power supply circuit.
标签： 9320 datasheet one-chip crystal
上传时间： 2014-11-21
上传用户：jiahao131
ST7787 芯片的SPEC，比亚迪2.4inchLCM的SPEC。The ST7787 is a single-chip controller/driver for 262K-color, graphic type TFT-LCD. It consists of 720 source line and 320 gate line driving circuits. This chip is capable of connecting directly to an external microprocessor, and accepts Serial Peripheral Interface (SPI), 8-bits/9-bits/16-bits/18-bits parallel interface. Display data can be stored in the on-chip display data RAM of 240x320x18 bits. It can perform display data RAM read/write operation with no external operation clock to minimize power consumption. In addition, because of the integrated power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
上传时间： 2016-09-22
上传用户：woshini123456
红外在单片机上的应用,C语言源码,Keil uVision3工程文件,附原理图及说明学习文档 红外接收电路采用集成红外接收器成品H1，接收器包括红外接收管和信号处理IC，均集成在红外接收器H1内。接收器对外只有3个引脚：Vcc、GND和一个脉冲信号输出PO。Vcc接系统的电源正极（+5V），GND接系统的地线，脉冲信号输出接CPU的中断输入引脚INT0。如果没有红外遥控信号到来，接收器的输出端口PO保持高电平，当接收到红外遥控信号时，接收器件信号转换成脉冲序列加到CPU的中断输入引脚。CPU定时器T0、T1都初始化为定时器工作方式1，T0的gate位置位，这样T0只在INT0为高电平时计数。每次外部中断首先停止定时，记录T0、T1的计数值，然后将T0、T1的计数器清零，并重新启动定时。T0的值即为高电平脉冲，T1－T0的值为低电平脉宽。 红外发送电路是将单片机发送的信号（P2.7管脚），由一个38K的脉冲频率进行调制，并通过一个红外发射管发送出去。U11B和U11C及附加的电阻电容形成了一个38K脉冲发生器。
上传时间： 2014-12-06
上传用户：风之骄子
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
标签： technology 2.0 USB designed
上传时间： 2014-01-01
上传用户：二驱蚊器
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
标签： technology 2.0 USB designed
上传时间： 2017-07-05
上传用户：zhoujunzhen
In this work an implementation of a geometric nonlinear controller for chaos synchronization in a Field Programmable gate Array (FPGA) is presented. The Lorenz chaotic system is used to show the implementation of chaos synchronization via nonlinear controller implemented in a Xilinx FPGA Virtex-II 2v2000ft896-4. The main idea is to design a nonlinear geometric controller which synchronizes a slave Lorenz system to a master system and then implement them into the FPGA.
标签： synchronization implementation controller geometric
上传时间： 2013-12-16
上传用户：3到15
In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field Programmable gate Array (FPGA). The aim of this method is to increase the frequency of the chaotic generators. The new method is based on the MATLAB® Software, Xilinx System Generator, Xilinx Alliance tools and Synplicity Synplify.
标签： introduced generators implement chaotic
上传时间： 2017-07-24
上传用户：qq521
