搜索结果
找到约 17 项符合
divider 的查询结果
按分类筛选
VHDL/FPGA/Verilog VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..
VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..
系统设计方案 PLL system LPF/PFD/VCO/Divider model in Matlab,在Matlab中将PLL系统的各个模块模型话
PLL system LPF/PFD/VCO/Divider model in Matlab,在Matlab中将PLL系统的各个模块模型话，便于分析整个PLL的环路稳定特性，锁定时间等…… 附录中包含完整的Matlab code
VHDL/FPGA/Verilog verilog code radix-2 SRT divider input [7:0]Dividend input [3:0]Divisor output [4:0]Quotient
verilog code
radix-2 SRT divider
input [7:0]Dividend
input [3:0]Divisor
output [4:0]Quotient
output [8:0]Remainder
VHDL/FPGA/Verilog a divider design based on verilog language
a divider design based on verilog language
编译器/解释器 multiplier and divider verilog codes
multiplier and divider verilog codes
其他 program to perform sequential divider in vhdl
program to perform sequential divider in vhdl
行业发展研究 DDS divider clock AHDL
DDS divider clock AHDL
其他 this file is divider vhdl program
this file is divider vhdl program
VHDL/FPGA/Verilog It is n-bit sequential divider in verilog language
It is n-bit sequential divider in verilog language
电源技术 开关稳压器的偏置低噪声变容
 
Telecommunication, satellite links and set-top boxes allrequire tuning a high frequency oscillator. The actualtuning element is a varactor diode, a 2-terminal device thatchanges capacitance as a function of reverse bias voltage.1 The oscillator is part of a frequency synthesizingloop, as ...